Towards Efficient Hyperdimensional Computing Using Photonics

TL;DR

This paper proposes PhotoHDC, the first-ever electro-photonic accelerator for HDC training and inference, supporting the basic, record-based, and graph encoding schemes, and shows that this accelerator can achieve two to five orders of magnitude lower EDP than the state-of-the-art electro-Photonic DNN accelerators for implementing HDCTraining and inference.

Abstract

Over the past few years, silicon photonics-based computing has emerged as a promising alternative to CMOS-based computing for Deep Neural Networks (DNN). Unfortunately, the non-linear operations and the high-precision requirements of DNNs make it extremely challenging to design efficient silicon photonics-based systems for DNN inference and training. Hyperdimensional Computing (HDC) is an emerging, brain-inspired machine learning technique that enjoys several advantages over existing DNNs, including being lightweight, requiring low-precision operands, and being robust to noise introduced by the nonidealities in the hardware. For HDC, computing in-memory (CiM) approaches have been widely used, as CiM reduces the data transfer cost if the operands can fit into the memory. However, inefficient multi-bit operations, high write latency, and low endurance make CiM ill-suited for HDC. On the other hand, the existing electro-photonic DNN accelerators are inefficient for HDC because they are specifically optimized for matrix multiplication in DNNs and consume a lot of power with high-precision data converters. In this paper, we argue that photonic computing and HDC complement each other better than photonic computing and DNNs, or CiM and HDC. We propose PhotoHDC, the first-ever electro-photonic accelerator for HDC training and inference, supporting the basic, record-based, and graph encoding schemes. Evaluating with popular datasets, we show that our accelerator can achieve two to five orders of magnitude lower EDP than the state-of-the-art electro-photonic DNN accelerators for implementing HDC training and inference. PhotoHDC also achieves four orders of magnitude lower energy-delay product than CiM-based accelerators for both HDC training and inference.

Figures (12)

• Figure 1: An illustration of the HDC training and inference processes with the traditional encoding scheme.
• Figure 2: An overview of the three HDC encoding schemes: traditional, record-based, and graph encoding.
• Figure 3: Dot product of vectors $\mathbf{A}$ and $\mathbf{B}$ using MZMs and PDs.
• Figure 4: Overview of the PhotoHDC accelerator microarchitecture consisting of an $R\times C$ photonic unit, data converters, SRAM-based memory units, and other circuits. The photonic unit uses one MZM per column to modulate the BHVs or CHVs and a PD array of $R$ rows and $C$ columns to perform multiplication with corresponding input values.
• Figure 5: Dataflow of HDC training with PhotoHDC for traditional and record-based/graph encoding methods (figure shows the processing of the first 2C features). The PD array processes the input values tile by tile, and for each tile, the MZMs modulate the corresponding BHV portions. Partial encoding results are generated in every row and bundling is performed by summing the row currents. ($\phi_j ^i$ indicates $\phi_j(\mathbf{x}^i)$).