Neuromorphic Intermediate Representation: A Unified Instruction Set for Interoperable Brain-Inspired Computing

TL;DR

NIR (Neuromorphic Intermediate Representation) is a model-centric, platform-agnostic intermediate representation for brain-inspired computing that expresses computations as hybrid continuous-time dynamics and discrete events. It defines 11 computational primitives organized as modeled by differential equations and discrete transitions, encoded as graphs with ports and edges to enable cross-platform interoperability. The authors demonstrate NIR across 11 backends (7 software simulators and 4 hardware platforms) on three networks: a LIF neuron, a spiking CNN, and a CuBa-LIF SRNN, showing high fidelity for feed-forward dynamics and noting mismatches in recurrent setups due to discretization and timing differences. The work argues that NIR decouples hardware and software development, provides a stable reference for benchmarking, and advances energy-efficient, platform-agnostic neuromorphic computing.

Abstract

Spiking neural networks and neuromorphic hardware platforms that simulate neuronal dynamics are getting wide attention and are being applied to many relevant problems using Machine Learning. Despite a well-established mathematical foundation for neural dynamics, there exists numerous software and hardware solutions and stacks whose variability makes it difficult to reproduce findings. Here, we establish a common reference frame for computations in digital neuromorphic systems, titled Neuromorphic Intermediate Representation (NIR). NIR defines a set of computational and composable model primitives as hybrid systems combining continuous-time dynamics and discrete events. By abstracting away assumptions around discretization and hardware constraints, NIR faithfully captures the computational model, while bridging differences between the evaluated implementation and the underlying mathematical formalism. NIR supports an unprecedented number of neuromorphic systems, which we demonstrate by reproducing three spiking neural network models of different complexity across 7 neuromorphic simulators and 4 digital hardware platforms. NIR decouples the development of neuromorphic hardware and software, enabling interoperability between platforms and improving accessibility to multiple neuromorphic technologies. We believe that NIR is a key next step in brain-inspired hardware-software co-evolution, enabling research towards the implementation of energy efficient computational principles of nervous systems. NIR is available at neuroir.org

Figures (5)

• Figure 1: High-level overview of NIR. (a) NIR allows for continuous-time representation of specific models that can then be executed on continuous-time hardware or simulators, or discretized for use on discrete-time hardware or simulators. (b) A taxonomy of discrete and continuous time hardware and simulators. Some representative hardware systems are shown. Analog Continuous Time: BrainDrop neckar2018braindrop, DYNAP-SE moradi2017scalable, and emerging technologies. These systems are greyed out because they are not covered in the present paper. Analog Discrete Time: NeuRRAM wan2022compute, UMich RRAM-IMC cai2019fully. Digital Continuous Time: Akida, SpiNNaker 1/2 Furber_Galluppi_Temple_Plana_2014mayr2019spinnaker, Speck. Note that we include chips with asynchronous routing in this category. Digital Discrete Time: Generic FPGA-based SNN Accelerators, ReckOn frenkel2022reckon, Xylo bos2023sub.
• Figure 2: Composition of primitives and their mapping to and from software and hardware systems. (a-d) shows four NIR primitives, where the name of the primitive is highlighted on top, the implemented computation is illustrated in the white box, and the parameters that are stored with the NIR graph are highlighted on the bottom. (a) shows a stateful primitive, while (b) and (c) show stateless primitives, and (d) shows a higher-order primitive. (e-f) illustrate the concept of an intermediate representation (IR) with 7 software (SW) and 4 hardware (HW) backends. Instead of 30 different compilers covering all $m \times n$ cases (e), only $m+n$ interfaces between each hardware and software platform to NIR are necessary (f).
• Figure 3: Computational graphs and sample data used in the experiments. (a) A single leaky integrate-and-fire neuron model (LIF), (b) a recurrent Braille classification model using current-based leaky integrate-and-fire (CuBa-LIF) in a spiking recurrent neural network (SRNN), and (c) a spiking convolutional neural network (SCNN). (d) and (e) shows sample data for the N-MNIST and Braille datasets, respectively. The N-MNIST activity is averaged across 300 timesteps.
• Figure 4: Experimental results. (a) Single leaky integrate-and fire neuron ordered from top to bottom on different platforms: input spikes, voltage traces, and output activations. The timestep of spikes are well-aligned and only differ systematically for Rockpool and Sinabs due to discretization differences. Membrane potentials are normalized to lie between the resting potential $v_{rest}=0$ and the firing threshold $\vartheta$ to ignore platform-specific details regarding the numerical representations. (b) Spiking convolutional neural network: a platform-by-platform comparison of the spiking activity from the first spiking layer using cosine similarity (1 equals perfect overlap). Sinabs, snnTorch and Speck deviate from most other implementations due to their discretization choices. (c) and (d) Spiking recurrent neural network: similarity measure between the spiking activity of the first CuBa-LIF layer for an SRNN with biases and reset to zero and an SRNN without biases and subtractive reset. See main text for details on the similarity metrics.
• Figure 5: Left: a signal flow graph where a signal $X$ is integrated by some arbitrary process to produce the output signal, $Y$. Right: a Mealy machine where a transition node $T$ updates a recurrent state $S$ that is forwarded to an output node $O$ which, in turn, determines the output $Y$.