PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors

TL;DR

This paper tackles energy efficiency in ultra-low-power IoT by addressing peripheral linking and wake-up overhead. It introduces PELS, a microcode-based peripheral event linking system that combines instant actions and sequenced actions via a tiny I/O processor integrated into a RISC-V platform. The authors demonstrate that PELS reduces the power per linking event by a factor of $2.5$ and requires a small silicon area (about $7$ kGE in its minimal configuration) when implemented in a ULP IoT processor, with scalable performance up to multiple parallel links. Compared with software interrupts and fixed event interconnects, PELS offers low latency and high flexibility without extensive peripheral redesign, enabling more predictable and energy-efficient inter-peripheral interactions.

Abstract

A key challenge for ultra-low-power (ULP) devices is handling peripheral linking, where the main central processing unit (CPU) periodically mediates the interaction among multiple peripherals following wake-up events. Current solutions address this problem by either integrating event interconnects that route single-wire event lines among peripherals or by general-purpose I/O processors, with a strong trade-off between the latency, efficiency of the former, and the flexibility of the latter. In this paper, we present an open-source, peripheral-agnostic, lightweight, and flexible Peripheral Event Linking System (PELS) that combines dedicated event routing with a tiny I/O processor. With the proposed approach, the power consumption of a linking event is reduced by 2.5 times compared to a baseline relying on the main core for the event-linking process, at a low area of just 7 kGE in its minimal configuration, when integrated into a ULP RISC-V IoT processor.

Figures (6)

• Figure 1: Profiles of different solutions for handling inter-peripheral communication in . (a) Traditional software interrupt approach. The main is woken up at each inter-peripheral event. (b) Configurable event-interconnect approach with minimal processing capability. The processing domain is bypassed and can sleep, while the event interconnect assures low latency but requires joint codesign with the peripheral system, affecting flexibility. (c) Proposed design that combines single-wire event lines and sequenced actions through the interconnect. doesn't require a priori knowledge of the peripheral system and trades off the low latency and flexibility of existing approaches. (\ref{['sec:evaluation']}).
• Figure 2: Architectural overview of a single link. The figure highlights the execution unit microarchitecture.
• Figure 3: Pseudocode showing 's flexibility in providing both sequenced and instant actions and associated latency in clock cycles.
• Figure 4: integration in PULPissimo .
• Figure 5: Power estimation with iso-latency and iso-frequency conditions between and Ibex.