Real-Time Adaptive Neural Network on FPGA: Enhancing Adaptability through Dynamic Classifier Selection
Achraf El Bouazzaoui, Abdelkader Hadjoudja, Omar Mouhib
TL;DR
The work addresses balancing accuracy and resource usage for FPGA-based neural networks deployed in edge settings. It introduces a Dynamic Classifier Selection (DCS) framework that uses a k-NC competence estimator to route each test instance to the most suitable neural network from a diverse, partially reconfigurable ensemble, formalized with a distance metric $d(x, C) = \\sqrt{\\sum_{i=1}^{n} (x_i - C_i)^2}$. Across three datasets, the DCS approach yields up to 8% improvements over the best single model, while achieving substantial hardware efficiency gains through partial reconfiguration on an Ultra96-V2 FPGA. This demonstrates the practical viability of FPGA-based adaptive ensembles for edge computing, combining real-time model adaptation with hardware-level efficiency.
Abstract
This research studies an adaptive neural network with a Dynamic Classifier Selection framework on Field-Programmable Gate Arrays (FPGAs). The evaluations are conducted across three different datasets. By adjusting parameters, the architecture surpasses all models in the ensemble set in accuracy and shows an improvement of up to 8% compared to a singular neural network implementation. The research also emphasizes considerable resource savings of up to 109.28%, achieved via partial reconfiguration rather than a traditional fixed approach. Such improved efficiency suggests that the architecture is ideal for settings limited by computational capacity, like in edge computing scenarios. The collected data highlights the architecture's two main benefits: high performance and real-world application, signifying a notable input to FPGA-based ensemble learning methods.