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RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures

Patrick Iff, Benigna Bruggmann, Blaise Morel, Maciej Besta, Luca Benini, Torsten Hoefler

TL;DR

RapidChiplet tackles the enormous design space of inter-chiplet interconnects in 2.5D chiplet systems by introducing high-level latency and throughput proxies that dramatically accelerate evaluation compared to cycle-based simulators. The toolchain combines a configurable core for proxy calculations, optional BookSim2 cycle-based simulations, automated design space exploration across chiplets, topologies, and traffic, and trace export/visualization utilities. Empirical evaluation shows order-of-magnitude to multi-order-of-magnitude speedups (e.g., latency proxy ~1075× with ~2.6% error; throughput proxy ~69,000× with ~25% error), enabling rapid screening of hundreds to hundreds of thousands of design points and informed Pareto-front analyses. A case study on SHG topology parametrizations demonstrates RapidChiplet’s capability to perform exhaustive searches that would be infeasible with traditional simulators, highlighting practical impact for fast, data-driven chiplet architecture optimization.

Abstract

Chiplet architectures are on the rise as they promise to overcome the scaling challenges of monolithic chips. A key component of such architectures is an efficient inter-chiplet interconnect (ICI). The ICI design space is huge as there are many degrees of freedom such as the number, size, and placement of chiplets, the topology and bandwidth of links, the packaging technology, and many more. While ICI simulators are important to get reliable performance estimates, they are not fast enough to explore hundreds of thousands of design points or to be used as a cost function for optimization algorithms or machine learning models. To address this issue, we present RapidChiplet, a fast and easy to use ICI latency and throughput prediction toolchain. Compared to cycle-level simulations, we trade 0.25%-30.15% of accuracy for 427x-137,682x speedup.

RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures

TL;DR

RapidChiplet tackles the enormous design space of inter-chiplet interconnects in 2.5D chiplet systems by introducing high-level latency and throughput proxies that dramatically accelerate evaluation compared to cycle-based simulators. The toolchain combines a configurable core for proxy calculations, optional BookSim2 cycle-based simulations, automated design space exploration across chiplets, topologies, and traffic, and trace export/visualization utilities. Empirical evaluation shows order-of-magnitude to multi-order-of-magnitude speedups (e.g., latency proxy ~1075× with ~2.6% error; throughput proxy ~69,000× with ~25% error), enabling rapid screening of hundreds to hundreds of thousands of design points and informed Pareto-front analyses. A case study on SHG topology parametrizations demonstrates RapidChiplet’s capability to perform exhaustive searches that would be infeasible with traditional simulators, highlighting practical impact for fast, data-driven chiplet architecture optimization.

Abstract

Chiplet architectures are on the rise as they promise to overcome the scaling challenges of monolithic chips. A key component of such architectures is an efficient inter-chiplet interconnect (ICI). The ICI design space is huge as there are many degrees of freedom such as the number, size, and placement of chiplets, the topology and bandwidth of links, the packaging technology, and many more. While ICI simulators are important to get reliable performance estimates, they are not fast enough to explore hundreds of thousands of design points or to be used as a cost function for optimization algorithms or machine learning models. To address this issue, we present RapidChiplet, a fast and easy to use ICI latency and throughput prediction toolchain. Compared to cycle-level simulations, we trade 0.25%-30.15% of accuracy for 427x-137,682x speedup.
Paper Structure (26 sections, 3 equations, 6 figures)

This paper contains 26 sections, 3 equations, 6 figures.

Table of Contents

  1. Introduction
  2. The RapidChiplet Toolchain
  3. RapidChiplet Core
  4. Inputs and Validation
  5. Latency Proxy
  6. Throughput Proxy
  7. Area, Power, and Cost Reports
  8. Cycle-based Simulations using BookSim2
  9. Automated Design Space Exploration
  10. Chiplets
  11. Placements
  12. ICI Topologies
  13. Routing Tables
  14. Traffic
  15. Exporting Traffic Traces using Netrace
  16. ...and 11 more sections

Figures (6)

  • Figure 1: (§ \ref{['sec:rc']}) RapidChiplet architecture overview.
  • Figure 2: (§ \ref{['sssec:rc-core-inputs']}) Overview of RapidChiplet input files and how they reference each other.
  • Figure 3: (§ \ref{['sssec:rc-dse-chiplets']}) Available PHY placements
  • Figure 4: (§ \ref{['ssec:rc-vis']}) Visualized design (left); results-plot (right).
  • Figure 5: (§ \ref{['ssec:eval-results']}) Evaluation of RapidChiplet's latency and throughput proxies compared to simulations in BookSim2.
  • ...and 1 more figures