CMOS-Compatible Electrostatic SWAP Gate in Silicon Quantum Dots: Justification of Tight-Binding Model and Going Beyond

TL;DR

This work develops a CMOS-compatible, electrostatically controlled two-double-dot chain as a generalized SWAP gate for position-based qubits in silicon quantum dots. It employs a minimalist tight-binding model with detuning and barrier controls, and derives analytic eigenvalues/eigenvectors and density matrices for symmetric and asymmetric Coulomb couplings, validating key predictions numerically and outlining a route to scalable, all-electrostatic quantum logic. A systematic procedure links classical electrostatic logic to quantum gates, including symmetric and antisymmetric swap regimes, correlation/anticorrelation criteria, and a quasiclassical perspective that guides circuit-design choices for large-scale semiconductor quantum-information processing. The study also discusses higher-order effects, entangled photon emission, and the limitations of the tight-binding picture, offering pathways to richer dynamics and CMOS-integrated quantum technologies.

Abstract

We present a generalized electrostatic SWAP gate realized in a chain of two double quantum dots operated in the single-electron regime. Using a minimalist tight-binding model, we derive analytical results and corroborate them with numerical simulations. We exploit the charge anticorrelation arising from Coulomb repulsion and quantify the resulting entanglement generation. We contrast classical and quantum descriptions and show how device geometry and coupling strengths govern entanglement dynamics and gate performance. The results are relevant to cryogenic, CMOS-compatible quantum technologies and suggest a route toward large-scale semiconductor implementations of quantum logic. Finally, we outline a systematic procedure for translating classical electrostatic logic gates into single-electron quantum gates.

Figures (20)

• Figure 1: Indicative scalability of selected qubit architectures. Stylized comparison of estimated qubits-per-die across superconducting, photonic, ion-trap and silicon spin platforms (based on public roadmaps from Diraq company https://diraq.com/).
• Figure 2: Representative implementations of silicon quantum dots and arrays (gate-defined MOS/SiGe, nanowires/holes, crossbar concepts, and 2D lattices). After Burkard et al., Rev. Mod. Phys. 95, 025003 (2023) BurkardRMP.
• Figure 3: Electrostatic, position-based qubit and tunable SWAP in a CMOS-compatible DQD (Double Quantum Dot) network; analytical treatment and numerical corroboration as by Pomorski Cryogenics.
• Figure 4: Scheme of electrostatically controlled qubit made from 2 neighbouring quantum dots and referring to the previous figure showing implementation of the single qubit.
• Figure 5: Scheme of electrostatic quantum gate as two interacting qubits (Pomorski_spieSELb3Cryogenicsb5) with geometrical parametrization of generalized electrostatic quantum gate.