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Quantization-aware Neural Architectural Search for Intrusion Detection

Rabin Yu Acharya, Laurens Le Jeune, Nele Mentens, Fatemeh Ganji, Domenic Forte

TL;DR

A design methodology that automatically trains and evolves quantized neural network (NN) models that are a thousand times smaller than state-of-the-art NNs but can efficiently analyze network data for intrusion at high accuracy is presented.

Abstract

Deploying machine learning-based intrusion detection systems (IDSs) on hardware devices is challenging due to their limited computational resources, power consumption, and network connectivity. Hence, there is a significant need for robust, deep learning models specifically designed with such constraints in mind. In this paper, we present a design methodology that automatically trains and evolves quantized neural network (NN) models that are a thousand times smaller than state-of-the-art NNs but can efficiently analyze network data for intrusion at high accuracy. In this regard, the number of LUTs utilized by this network when deployed to an FPGA is between 2.3x and 8.5x smaller with performance comparable to prior work.

Quantization-aware Neural Architectural Search for Intrusion Detection

TL;DR

A design methodology that automatically trains and evolves quantized neural network (NN) models that are a thousand times smaller than state-of-the-art NNs but can efficiently analyze network data for intrusion at high accuracy is presented.

Abstract

Deploying machine learning-based intrusion detection systems (IDSs) on hardware devices is challenging due to their limited computational resources, power consumption, and network connectivity. Hence, there is a significant need for robust, deep learning models specifically designed with such constraints in mind. In this paper, we present a design methodology that automatically trains and evolves quantized neural network (NN) models that are a thousand times smaller than state-of-the-art NNs but can efficiently analyze network data for intrusion at high accuracy. In this regard, the number of LUTs utilized by this network when deployed to an FPGA is between 2.3x and 8.5x smaller with performance comparable to prior work.
Paper Structure (18 sections, 2 equations, 4 figures, 3 tables)

This paper contains 18 sections, 2 equations, 4 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Intrusion Detection System (IDS)
  4. Deep Learning-based IDS
  5. Design Methodology
  6. InfoNEAT
  7. q-InfoNEAT
  8. Deployment in Hardware
  9. Results and Analysis
  10. Dataset
  11. Experimental Setup
  12. Results
  13. Impact of using imbalanced dataset
  14. Sensitivity to different $k$ folds of validation
  15. Learning curve
  16. ...and 3 more sections

Figures (4)

  • Figure 1: Overview of quantization aware training algorithm.
  • Figure 2: Learning curve of the InfoNEAT model with and without quantization across different generations during training.
  • Figure 3: Modification of the q-InfoNEAT model for FPGA deployment. The network on the left is a typical InfoNEAT model with its irregular architecture (such as a direct connection from layer 1 to layer 3). The network on the right is the modified model with an insertion of dummy nodes and connections (represented by dotted shapes) such that the resultant model resembles an MLP network. The number inside the shapes shows their corresponding layer number.
  • Figure 4: Comparison of training q-InfoNEAT model on balanced versus imbalanced UNSW-NB15 dataset.