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Symmetry-Based Quantum Circuit Mapping

Di Yu, Kun Fang

TL;DR

The paper tackles the scalability bottleneck of quantum circuit remapping by exploiting hardware symmetries to drastically prune the search space of isomorphic mappings. It introduces the symmetry-based subgraph matching (SBSM) algorithm and a vectorized circuit mapping scoring method, which together form the symmetry-based circuit mapping (SBCM) pipeline, achieving $O(n)$ time under bounded-degree graphs and offering theoretical optimality. Empirical benchmarks across grid, octagonal, and heavy-hex architectures show large speedups over state-of-the-art approaches like VF2/VF2++ and MAPOMATIC, including dramatic reductions in runtime for large-scale devices with up to tens of thousands of qubits. The work has practical impact for compiling circuits onto future quantum processors with millions of qubits and suggests broad applicability of hardware symmetry in quantum compilation and beyond.

Abstract

Quantum circuit mapping is a crucial process in the quantum circuit compilation pipeline, facilitating the transformation of a logical quantum circuit into a list of instructions directly executable on a target quantum system. Recent research has introduced a post-compilation step known as remapping, which seeks to reconfigure the initial circuit mapping to mitigate quantum circuit errors arising from system variability. As quantum processors continue to scale in size, the efficiency of quantum circuit mapping and the overall compilation process has become of paramount importance. In this work, we introduce a quantum circuit remapping algorithm that leverages the intrinsic symmetries in quantum processors, making it well-suited for large-scale quantum systems. This algorithm identifies all topologically equivalent circuit mappings by constraining the search space using symmetries and accelerates the scoring of each mapping using vector computation. Notably, this symmetry-based circuit remapping algorithm exhibits linear scaling with the number of qubits in the target quantum hardware and is proven to be optimal in terms of its time complexity. Moreover, we conduct a comparative analysis against existing methods in the literature, demonstrating the superior performance of our symmetry-based method on state-of-the-art quantum hardware architectures and highlighting the practical utility of our algorithm, particularly for quantum processors with millions of qubits.

Symmetry-Based Quantum Circuit Mapping

TL;DR

The paper tackles the scalability bottleneck of quantum circuit remapping by exploiting hardware symmetries to drastically prune the search space of isomorphic mappings. It introduces the symmetry-based subgraph matching (SBSM) algorithm and a vectorized circuit mapping scoring method, which together form the symmetry-based circuit mapping (SBCM) pipeline, achieving time under bounded-degree graphs and offering theoretical optimality. Empirical benchmarks across grid, octagonal, and heavy-hex architectures show large speedups over state-of-the-art approaches like VF2/VF2++ and MAPOMATIC, including dramatic reductions in runtime for large-scale devices with up to tens of thousands of qubits. The work has practical impact for compiling circuits onto future quantum processors with millions of qubits and suggests broad applicability of hardware symmetry in quantum compilation and beyond.

Abstract

Quantum circuit mapping is a crucial process in the quantum circuit compilation pipeline, facilitating the transformation of a logical quantum circuit into a list of instructions directly executable on a target quantum system. Recent research has introduced a post-compilation step known as remapping, which seeks to reconfigure the initial circuit mapping to mitigate quantum circuit errors arising from system variability. As quantum processors continue to scale in size, the efficiency of quantum circuit mapping and the overall compilation process has become of paramount importance. In this work, we introduce a quantum circuit remapping algorithm that leverages the intrinsic symmetries in quantum processors, making it well-suited for large-scale quantum systems. This algorithm identifies all topologically equivalent circuit mappings by constraining the search space using symmetries and accelerates the scoring of each mapping using vector computation. Notably, this symmetry-based circuit remapping algorithm exhibits linear scaling with the number of qubits in the target quantum hardware and is proven to be optimal in terms of its time complexity. Moreover, we conduct a comparative analysis against existing methods in the literature, demonstrating the superior performance of our symmetry-based method on state-of-the-art quantum hardware architectures and highlighting the practical utility of our algorithm, particularly for quantum processors with millions of qubits.
Paper Structure (16 sections, 7 theorems, 5 figures, 3 algorithms)

This paper contains 16 sections, 7 theorems, 5 figures, 3 algorithms.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Notation
  4. Symmetry of graph
  5. Graph distance
  6. Quantum circuit mapping
  7. Symmetry-Based Quantum Circuit Mapping
  8. Symmetry-based subgraph matching
  9. Circuit mapping scoring through vectorization
  10. Symmetry-based quantum circuit mapping
  11. Computational complexity
  12. Benchmarking Results
  13. Benchmarking the subgraph matching algorithms
  14. Benchmarking the circuit mapping scoring methods
  15. Benchmarking the complete circuit mapping algorithms
  16. ...and 1 more sections

Key Result

Theorem 1

Let $T$ be a graph and $S$ be a generating set of $T$ with respect to the automorphism $f$. Let $G$ be a subgraph of $T$ with radius $r$. Then for any subgraph $G"$ of $T$ that is isomorphic to $G$, there exists an integer $n$ and subgraph $G'\subseteq T$ such that $G" = \tilde{f}^n(G')$ with $G' \c

Figures (5)

  • Figure 1: An illustration of quantum circuit compilation with mapping and remapping processes. (a) The input quantum circuit. (b) The precompiled quantum circuit, assuming {U3, CX, SWAP} as the set of native operations in this example. (c) The interaction graph of the precompiled circuit. (d) A coupling graph with the heavy-hex structure. The mapping process finds a mapping from logical qubits in the interaction graph to physical qubits in the coupling graph. The remapping process finds a mapping from physical qubits to physical qubits such that the composed mapping-and-remapping process reduces the error of circuit implementation. The search for all isomorphic subgraphs employed in the remapping process can be confined to the reduced search space, which is a neighborhood of the generating set, as depicted within the red area.
  • Figure 2: Three typical quantum chip structures. Each node represents a physical qubit, and each edge corresponds to a coupler between two qubits. (a) $7 \times 7$ grid coupling graph with $49$ qubits. (b) $3 \times 3$ octagonal coupling graph with $72$ qubits. (c) $4 \times 2$ heavy-hex coupling graph with $67$ qubits.
  • Figure 3: The runtime of three subgraph matching algorithms: VF2 (green) cordella2004sub, VF2++ (blue) juttner2018vf2++, and the SBSM algorithm (red). These experiments solved the subgraph matching problem on three quantum hardware architectures. Note that the results for VF2 and VF2++ coincide in the first plot.
  • Figure 4: The runtime for scoring circuit mappings using the conventional for-loop method in MAPOMATIC (blue) nation2023suppressing and our vectorized approach (red). These experiments were conducted on three distinct quantum hardware architectures.
  • Figure 5: The runtime of two circuit remapping algorithms: MAPOMATIC (blue) nation2023suppressing and SBCM (red). These experiments were conducted on three distinct quantum hardware architectures.

Theorems & Definitions (7)

  • Theorem 1
  • Lemma 2
  • Lemma 3
  • Corollary 4
  • Theorem 5
  • Lemma 6
  • Corollary 7