Generalized Staircase Codes with Arbitrary Bit Degree
Mohannad Shehadeh, Frank R. Kschischang, Alvin Y. Sukmadji
TL;DR
The paper addresses the energy-efficient high-rate FEC problem by generalizing staircase codes to give each bit protection from $M+1$ component codes. It presents a detailed construction using memory $M$, $M+1$ permutations, a Golomb ruler, and an $(M+1,S)$-net to ensure at-most-one-bit intersections and sub-TeV-level error floors, while recovering classical staircase codes at $M=1$. The nominal and practical block rates are $R_\mathsf{nominal}=1-\frac{r}{S}$ and $R=\frac{(S-r)(F-W)}{S(F-W)+Wr}$, with a sliding-window decoder and termination-like framing. Simulations with extended Hamming components show sub-$10^{-15}$ BER floors and a modest gap ($\sim$0.2–0.5 dB) to the hard-decision Shannon limit compared to two triple-error-correcting BCH-based staircases, indicating substantial potential for energy-efficient, high-throughput FEC.
Abstract
We introduce a natural generalization of staircase codes in which each bit is protected by arbitrarily many component codewords rather than two. This enables powerful energy-efficient FEC based on iterative decoding of Hamming components.