An On-Chip Trainable Neuron Circuit for SFQ-Based Spiking Neural Networks

TL;DR

This work presents an on-chip trainable neuron circuit that aims at bio-inspired spike-based time-dependent data computation for training spiking neural networks (SNN).

Abstract

We present an on-chip trainable neuron circuit. Our proposed circuit suits bio-inspired spike-based time-dependent data computation for training spiking neural networks (SNN). The thresholds of neurons can be increased or decreased depending on the desired application-specific spike generation rate. This mechanism provides us with a flexible design and scalable circuit structure. We demonstrate the trainable neuron structure under different operating scenarios. The circuits are designed and optimized for the MIT LL SFQ5ee fabrication process. Margin values for all parameters are above 25\% with a 3GHz throughput for a 16-input neuron.

Figures (9)

• Figure 1: Neuron Circuit Block Diagram with TAU, TU, and arbiter. The TA has increment and decrement pins that adjust the load value. The arbiter then applies this load value with the input signals to the TU, generating the output. Each output triggers the TAU to reload the data to the arbiter.
• Figure 2: Threshold Unit Cascading Structure. The threshold unit consists of a series of RTFFs. Adding one RTFF increases the maximum threshold by two.
• Figure 3: Simulations result of a TU with one RTFF, which means the threshold value of two.
• Figure 4: Simulations result of a TU with two RTFF, which means the threshold value of four.
• Figure 5: State Machine of TAU. When the circuit is in an Idle state, the clock signal generates no output, whereas the decrement signal maintains the idle state. Each increment signal advances the machine to a higher state; progressively more SFQ pulses are generated until the last state is reached.