Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources

TL;DR

Victima targets the address-translation bottleneck by repurposing underutilized L2 cache blocks to store TLB entries, creating a high-capacity, low-latency backing to the L2 TLB. It uses a PTW cost predictor (PTW-CP) to selectively cache translations for costly pages and a TLBCache-aware replacement policy to preserve TLB blocks. Across native and virtualized workloads, Victima delivers notable performance gains (native ~$7.4\%$, virtualized ~$28.7\%$) with negligible area/power costs (~$0.04\%$ area, ~$0.08\%$ power) and achieves up to $36\times$ translation reach (≈$220\,\mathrm{MB}$). The technique is hardware-conscious, software-transparent, and compatible with large pages, presenting a practical path to mitigate PTWs in data-intensive systems.

Abstract

Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). PTWs can be reduced by using (i) large hardware TLBs or (ii) large software-managed TLBs. Unfortunately, both solutions have significant drawbacks: increased access latency, power and area (for hardware TLBs), and costly memory accesses, the need for large contiguous memory blocks, and complex OS modifications (for software-managed TLBs). We present Victima, a new software-transparent mechanism that drastically increases the translation reach of the processor by leveraging the underutilized resources of the cache hierarchy. The key idea of Victima is to repurpose L2 cache blocks to store clusters of TLB entries, thereby providing an additional low-latency and high-capacity component that backs up the last-level TLB and thus reduces PTWs. Victima has two main components. First, a PTW cost predictor (PTW-CP) identifies costly-to-translate addresses based on the frequency and cost of the PTWs they lead to. Second, a TLB-aware cache replacement policy prioritizes keeping TLB entries in the cache hierarchy by considering (i) the translation pressure (e.g., last-level TLB miss rate) and (ii) the reuse characteristics of the TLB entries. Our evaluation results show that in native (virtualized) execution environments Victima improves average end-to-end application performance by 7.4% (28.7%) over the baseline four-level radix-tree-based page table design and by 6.2% (20.1%) over a state-of-the-art software-managed TLB, across 11 diverse data-intensive workloads. Victima (i) is effective in both native and virtualized environments, (ii) is completely transparent to application and system software, and (iii) incurs very small area and power overheads on a modern high-end CPU.

Figures (29)

• Figure 1: Four-level radix-tree page table walk in x86-64 ISA.
• Figure 2: Structure of the Memory Management Unit (MMU) of a modern processor.
• Figure 3: MMU extensions to support address translation in virtualized environments using Nested Paging amdnested.
• Figure 4: Distribution of PTW latency.
• Figure 5: L2 TLB MPKI for L2 TLBs with different sizes.