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Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

Michael Rogenmoser, Luca Benini

TL;DR

This work tackles radiation-induced single-event upsets in space by proposing Trikarenos, a fault-tolerant 32-bit RISC-V microcontroller implemented in 28nm. It uses a configurable triple-core Ibex lockstep with majority voting and ECC-protected memory to deliver reliable operation while reducing replication costs, and it supports a performance mode where cores run independently for higher throughput. Key contributions include a 256KiB ECC-protected memory with per-bank Hsiao coding and continuous memory scrubbing, dedicated design-for-testing facilities, and a detailed evaluation on matrix-matrix multiply benchmarks showing up to a $2.96×$ speedup and substantial energy-efficiency gains. The design offers a practical, scalable solution for CubeSats, balancing reliability, performance, and power in a compact, space-qualified 28nm implementation.

Abstract

One of the key challenges when operating microcontrollers in harsh environments such as space is radiation-induced Single Event Upsets (SEUs), which can lead to errors in computation. Common countermeasures rely on proprietary radiation-hardened technologies, low density technologies, or extensive replication, leading to high costs and low performance and efficiency. To combat this, we present Trikarenos, a fault-tolerant 32-bit RISC-V microcontroller SoC in an advanced TSMC 28nm technology. Trikarenos alleviates the replication cost by employing a configurable triple-core lockstep configuration, allowing three Ibex cores to execute applications reliably, operating on ECC-protected memory. If reliability is not needed for a given application, the cores can operate independently in parallel for higher performance and efficiency. Trikarenos consumes 15.7mW at 250MHz executing a fault-tolerant matrix-matrix multiplication, a 21.5x efficiency gain over state-of-the-art, and performance is increased by 2.96x when reliability is not needed for processing, with a 2.36x increase in energy efficiency.

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

TL;DR

This work tackles radiation-induced single-event upsets in space by proposing Trikarenos, a fault-tolerant 32-bit RISC-V microcontroller implemented in 28nm. It uses a configurable triple-core Ibex lockstep with majority voting and ECC-protected memory to deliver reliable operation while reducing replication costs, and it supports a performance mode where cores run independently for higher throughput. Key contributions include a 256KiB ECC-protected memory with per-bank Hsiao coding and continuous memory scrubbing, dedicated design-for-testing facilities, and a detailed evaluation on matrix-matrix multiply benchmarks showing up to a speedup and substantial energy-efficiency gains. The design offers a practical, scalable solution for CubeSats, balancing reliability, performance, and power in a compact, space-qualified 28nm implementation.

Abstract

One of the key challenges when operating microcontrollers in harsh environments such as space is radiation-induced Single Event Upsets (SEUs), which can lead to errors in computation. Common countermeasures rely on proprietary radiation-hardened technologies, low density technologies, or extensive replication, leading to high costs and low performance and efficiency. To combat this, we present Trikarenos, a fault-tolerant 32-bit RISC-V microcontroller SoC in an advanced TSMC 28nm technology. Trikarenos alleviates the replication cost by employing a configurable triple-core lockstep configuration, allowing three Ibex cores to execute applications reliably, operating on ECC-protected memory. If reliability is not needed for a given application, the cores can operate independently in parallel for higher performance and efficiency. Trikarenos consumes 15.7mW at 250MHz executing a fault-tolerant matrix-matrix multiplication, a 21.5x efficiency gain over state-of-the-art, and performance is increased by 2.96x when reliability is not needed for processing, with a 2.36x increase in energy efficiency.
Paper Structure (8 sections, 4 figures, 2 tables)

This paper contains 8 sections, 4 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Architecture
  3. Design for Testing
  4. Results
  5. Implementation
  6. Performance
  7. Related Work
  8. Conclusion

Figures (4)

  • Figure 1: Block Diagram of the Trikarenos , with the main additions for fault tolerance highlighted.
  • Figure 2: Trikarenos die image with overlayed component highlighting.
  • Figure 3: Power measurement results of a 24x24 32-bit Matrix multiplication for different configurations at maximum frequency for varying voltage.
  • Figure 4: Processing efficiency of a 24x24 32-bit matrix multiplication in different configurations at varying voltages, vs. processing performance.