DYNAP-SE2: a scalable multi-core dynamic neuromorphic asynchronous spiking neural network processor

TL;DR

DYNAP-SE2 presents a scalable, multi-core neuromorphic processor that tightly integrates analog neuronal/synaptic dynamics with an asynchronous, clock-free routing fabric for real-time edge processing of event-based signals. The architecture supports 1024 integrate-and-fire neurons across four cores, each with 64 synapses and four dendritic branches, while robust primitives such as DPI, pulse extenders, and NMDA/AMPA conductance dynamics enable biologically plausible temporal processing. A CAM/SRAM-based routing scheme, 2D sensor pre-processing, and on-chip sADCs facilitate flexible network topologies and direct sensor interfacing, complemented by the Samna software stack for unified control and remote experimentation. The work demonstrates hardware-measured neural dynamics, long-timescale adaptation and homeostasis, and rich synaptic/dendritic behavior, positioning DYNAP-SE2 as a practical platform for rapid prototyping and testing of complex neuromorphic models in edge computing scenarios.

Abstract

With the remarkable progress that technology has made, the need for processing data near the sensors at the edge has increased dramatically. The electronic systems used in these applications must process data continuously, in real-time, and extract relevant information using the smallest possible energy budgets. A promising approach for implementing always-on processing of sensory signals that supports on-demand, sparse, and edge-computing is to take inspiration from biological nervous system. Following this approach, we present a brain-inspired platform for prototyping real-time event-based Spiking Neural Networks (SNNs). The system proposed supports the direct emulation of dynamic and realistic neural processing phenomena such as short-term plasticity, NMDA gating, AMPA diffusion, homeostasis, spike frequency adaptation, conductance-based dendritic compartments and spike transmission delays. The analog circuits that implement such primitives are paired with a low latency asynchronous digital circuits for routing and mapping events. This asynchronous infrastructure enables the definition of different network architectures, and provides direct event-based interfaces to convert and encode data from event-based and continuous-signal sensors. Here we describe the overall system architecture, we characterize the mixed signal analog-digital circuits that emulate neural dynamics, demonstrate their features with experimental measurements, and present a low- and high-level software ecosystem that can be used for configuring the system. The flexibility to emulate different biologically plausible neural networks, and the chip's ability to monitor both population and single neuron signals in real-time, allow to develop and validate complex models of neural processing for both basic research and edge-computing applications.

Figures (25)

• Figure 1: Photo of the DYNAP-SE2 chip, which has an area of $98\,mm^2$ manufactured in 180nm CMOS technology as a cost effective prototyping platform.
• Figure 2: Neuronal compartments. 64 synapses with 4-bit weights and conditional delay and short-term plasticity (STP) convert pre-synaptic spikes to pulses. The pulses are low-pass-filtered by one of the four dendrites to generate post-synaptic currents (PSC). The dendrites have conditional alpha-function excitatory PSCs, a diffusive grid, membrane voltage gating and ion-channel conductances. The PSCs are injected into the soma, which can switch between a thresholded Rubino_etal19 and exponential integrate-and-fire model Brette_Gerstner05, with conditional adaptation and 'calcium'-based homeostasis. When the neuron fires, the AER spike is sent to up to four chips.
• Figure 3: One neural core with 256 neurons in a 16 $\times$ 16 array.
• Figure 4: N- and P-type DPI circuits and corresponding block diagrams. The output current $I_{out}$ can be thought of as a low-pass filtered version of the input current $I_{in}$. The circuit is designed in current mode, where $I_{x}$ ($x \in \{tau, gain, out\}$) is the current flowing in the diode-connected transistor with voltage $V_x$ of the corresponding type (for example $I_{out}$ and $V_{out}$ in the schematics).
• Figure 5: N- and P-type DPI with mirrored output. The new output $I_{out}$ flows in the opposite direction to the original one in Fig. \ref{['fig:dpi_circuit']} but has the same magnitude.