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SwiftSpatial: Spatial Joins on Modern Hardware

Wenqi Jiang, Oleh-Yevhen Khavrona, Martin Parvanov, Gustavo Alonso

TL;DR

SwiftSpatial introduces an FPGA-based accelerator for fast spatial joins, addressing the high performance cost of R-tree synchronous traversal and PBSM. The design uses multiple specialized join units with hybrid parallelism, an on-chip scheduler, and memory-management units to achieve low-latency tile-level joins at high throughput, while maintaining energy efficiency. It demonstrates up to 41.03× latency reduction and 6.16× power savings over the best software baselines, with strong scalability and reusability across data-center and embedded settings. This work suggests that hardware-accelerated spatial joins on FPGAs can significantly accelerate spatial data management workloads and enable flexible deployments beyond traditional CPU/GPU frameworks.

Abstract

Spatial joins are among the most time-consuming spatial queries, remaining costly even in parallel and distributed systems. In this paper, we explore hardware acceleration for spatial joins by proposing SwiftSpatial, an FPGA-based accelerator that can be deployed in data centers and at the edge. SwiftSpatial contains multiple high-performance join units with innovative hybrid parallelism, several efficient memory management units, and an extensible on-chip join scheduler that supports the popular R-tree synchronous traversal and partition-based spatial-merge (PBSM) algorithms. Benchmarked against various CPU and GPU-based spatial data processing systems, SwiftSpatial demonstrates a latency reduction of up to 41.03x relative to the best-performing baseline, while requiring 6.16x less power. The performance and energy efficiency of SwiftSpatial demonstrate its potential to be used in a variety of configurations (e.g., as an accelerator, near storage, in-network) as well as on different devices (e.g., data centers where FPGAs are widely available or mobile devices, which also contain FPGAs for specialized processing).

SwiftSpatial: Spatial Joins on Modern Hardware

TL;DR

SwiftSpatial introduces an FPGA-based accelerator for fast spatial joins, addressing the high performance cost of R-tree synchronous traversal and PBSM. The design uses multiple specialized join units with hybrid parallelism, an on-chip scheduler, and memory-management units to achieve low-latency tile-level joins at high throughput, while maintaining energy efficiency. It demonstrates up to 41.03× latency reduction and 6.16× power savings over the best software baselines, with strong scalability and reusability across data-center and embedded settings. This work suggests that hardware-accelerated spatial joins on FPGAs can significantly accelerate spatial data management workloads and enable flexible deployments beyond traditional CPU/GPU frameworks.

Abstract

Spatial joins are among the most time-consuming spatial queries, remaining costly even in parallel and distributed systems. In this paper, we explore hardware acceleration for spatial joins by proposing SwiftSpatial, an FPGA-based accelerator that can be deployed in data centers and at the edge. SwiftSpatial contains multiple high-performance join units with innovative hybrid parallelism, several efficient memory management units, and an extensible on-chip join scheduler that supports the popular R-tree synchronous traversal and partition-based spatial-merge (PBSM) algorithms. Benchmarked against various CPU and GPU-based spatial data processing systems, SwiftSpatial demonstrates a latency reduction of up to 41.03x relative to the best-performing baseline, while requiring 6.16x less power. The performance and energy efficiency of SwiftSpatial demonstrate its potential to be used in a variety of configurations (e.g., as an accelerator, near storage, in-network) as well as on different devices (e.g., data centers where FPGAs are widely available or mobile devices, which also contain FPGAs for specialized processing).
Paper Structure (32 sections, 1 equation, 16 figures, 2 tables, 4 algorithms)

This paper contains 32 sections, 1 equation, 16 figures, 2 tables, 4 algorithms.

Table of Contents

  1. Introduction
  2. Background and Motivation
  3. Spatial Join
  4. R-tree and Synchronous Traversal
  5. Partition-Based Spatial-Merge (PBSM)
  6. Existing Performance Optimizations
  7. Field Programmable Gate Arrays (FPGAs)
  8. SwiftSpatial: Accelerator Design
  9. Design Principles
  10. Accelerator Overview
  11. Join Units
  12. On-chip Scheduler
  13. Synchronous Traversal Scheduler
  14. PBSM Scheduler
  15. Memory Management
  16. ...and 17 more sections

Figures (16)

  • Figure 1: A two-level R-tree index containing six objects.
  • Figure 2: SwiftSpatial accelerator overview.
  • Figure 3: The microarchitecture design of a join unit.
  • Figure 4: The control flow of a SwiftSpatial join unit.
  • Figure 5: The control flow of the on-chip scheduler.
  • ...and 11 more figures