AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming

TL;DR

AxOMaP tackles the design of FPGA-based approximate arithmetic operators for ML-inference in resource-constrained systems by marrying data-driven statistical analysis with MIQCP optimization. The approach leverages correlation between LUT usage and performance/error metrics to steer a constrained multi-objective search, then augments evolutionary optimization with data-guided seeds to generate robust Pareto fronts. Empirical results show up to 116% improvement in Pareto-front hypervolume for operator-level DSE and up to 27% for application-specific DSE compared with state-of-the-art methods, demonstrating substantial gains in $PPA$ and BEHAV under realistic FPGA constraints. This framework enables more efficient, platform-aware approximate arithmetic design for embedded ML workloads, with potential for extension to richer operator models and analysis techniques.

Abstract

With the increasing application of machine learning (ML) algorithms in embedded systems, there is a rising necessity to design low-cost computer arithmetic for these resource-constrained systems. As a result, emerging models of computation, such as approximate and stochastic computing, that leverage the inherent error-resilience of such algorithms are being actively explored for implementing ML inference on resource-constrained systems. Approximate computing (AxC) aims to provide disproportionate gains in the power, performance, and area (PPA) of an application by allowing some level of reduction in its behavioral accuracy (BEHAV). Using approximate operators (AxOs) for computer arithmetic forms one of the more prevalent methods of implementing AxC. AxOs provide the additional scope for finer granularity of optimization, compared to only precision scaling of computer arithmetic. To this end, designing platform-specific and cost-efficient approximate operators forms an important research goal. Recently, multiple works have reported using AI/ML-based approaches for synthesizing novel FPGA-based AxOs. However, most of such works limit usage of AI/ML to designing ML-based surrogate functions used during iterative optimization processes. To this end, we propose a novel data analysis-driven mathematical programming-based approach to synthesizing approximate operators for FPGAs. Specifically, we formulate mixed integer quadratically constrained programs based on the results of correlation analysis of the characterization data and use the solutions to enable a more directed search approach for evolutionary optimization algorithms. Compared to traditional evolutionary algorithms-based optimization, we report up to 21% improvement in the hypervolume, for joint optimization of PPA and BEHAV, in the design of signed 8-bit multipliers.

Figures (19)

• Figure 1: Correlation between LUT usage and, PDPLUT and AVG_ABS_REL_ERR for approximate signed $4 \times 4$ multiplier designs obtained by selective LUT removal
• Figure 2: Comparing the R2 score of the polynomial regression models of PDPLUT and AVG_ABS_REL_ERR of approximate signed $4 \times 4$ multipliers with an increasing number of quadratic terms
• Figure 3: Approximating a $3-bit$ unsigned adder's FPGA implementation using selective LUT removal
• Figure 4: Methodology
• Figure 5: Distribution of the PDPLUT and AVG_ABS_REL_ERR for 1024 approximate signed $4\times 4$ multipliers generated using the operator model proposed in ullah2022appaxo