Computational Capabilities and Compiler Development for Neutral Atom Quantum Processors: Connecting Tool Developers and Hardware Experts

TL;DR

Neutral Atom Quantum Computing (NAQC) offers long coherence, long-range connectivity via Rydberg blockade, native multi-qubit gates, and dynamic atom shuttling, but requires hardware-aware software to translate high-level algorithms into hardware-executable instructions. This work surveys the NAQC platform, derives hardware-specific constraints and figures of merit, and presents a comprehensive view of compilation steps—synthesis, mapping, and scheduling—across multiple capability paths (nearest-neighbor, long-range, multi-qubit gates, and shuttling). Through selected case studies and error analyses, it demonstrates how hardware parameters influence compilation outcomes and proposes a flexible, hardware-aware framework for tool developers and hardware experts to co-design future compilers and hardware configurations. The findings advocate hybrid, adaptive compilation strategies that exploit the full spectrum of NAQC capabilities, with an eye toward fault-tolerant quantum computing and scalable design automation.

Abstract

Neutral Atom Quantum Computing (NAQC) emerges as a promising hardware platform primarily due to its long coherence times and scalability. Additionally, NAQC offers computational advantages encompassing potential long-range connectivity, native multi-qubit gate support, and the ability to physically rearrange qubits with high fidelity. However, for the successful operation of a NAQC processor, one additionally requires new software tools to translate high-level algorithmic descriptions into a hardware executable representation, taking maximal advantage of the hardware capabilities. Realizing new software tools requires a close connection between tool developers and hardware experts to ensure that the corresponding software tools obey the corresponding physical constraints. This work aims to provide a basis to establish this connection by investigating the broad spectrum of capabilities intrinsic to the NAQC platform and its implications on the compilation process. To this end, we first review the physical background of NAQC and derive how it affects the overall compilation process by formulating suitable constraints and figures of merit. We then provide a summary of the compilation process and discuss currently available software tools in this overview. Finally, we present selected case studies and employ the discussed figures of merit to evaluate the different capabilities of NAQC and compare them between two hardware setups.

Figures (13)

• Figure 1: Illustration of the three steps for platform-dependent compilation. In the synthesis step, general operations and unitaries are decomposed into the native gate set $\Sigma_{\mathrm{native}}$. During the mapping step, the circuit qubits $q_{i}$ are assigned to physical hardware qubits $Q_{i}$, and necessary SWAP or MOVE operations are introduced to satisfy connectivity constraints. Finally, in the scheduling step, gate times and restrictions on parallelism are considered. In practice, these steps are often performed simultaneously as a single step rather than sequentially.
• Figure 2: Capabilities of the NAQC platform. In this setup, atoms are arranged on a regular grid of Spatial Light Modulator (SLM) traps, with a fixed distance denoted as $d$. (a) Rydberg blockade interaction: Within a specific interaction zone of radius $r_{\mathrm{int}} = \sqrt{2}d$, depicted in yellow, interacting gates can be performed to all qubits within this range. (b) Two-qubit gate: A gate can be applied between neighboring qubits but restricts the simultaneous execution of other entangling gates on nearby atoms. The restriction volume, represented by a red sphere of radius $r_{\mathrm{re}} = d$, indicates this restriction. The interaction radius $r_{\mathrm{int}}=d$ is not explicitly shown to simplify the illustration. (c) Long-Range interactions: For gates with larger interaction radii, the restriction zones ($r_{\mathrm{re}} = 3d \geq r_{\mathrm{int}} = 2\sqrt{2}d$) also expand, resulting in more restricted atoms. (d) CCZ gate with a line arrangement of the qubits. According to levine_2019_parallel it is sufficient if the central atom interacts with both the outer qubits, resulting in a minimal interaction radius of $r_\mathrm{int} = d$. The restriction radius is illustrated examplatory as $r_\mathrm{re}= 2d$. (e) CCCZ gate: In this case, we require that all four gate qubits must be within the interaction radius $r_{\mathrm{int}} = r_{\mathrm{re}}=2d$ of every other qubit, according to \ref{['eq:multi-qubit-mapping']}. (f) Shuttling operation: Dynamic Acousto-Optic Deflector (AOD) traps (blue) enable the movement of atoms within the same column ($x$) or row coordinate ($y$) simultaneously. The procedure addresses certain constraints discussed in \ref{['sec:atom-shuttling']}. (g) Additional NA capabilities, useful for future fault-tolerant computations. For example, mid-circuit measurements and possible inter-photonic connections.
• Figure 3: Neutral Atom Dynamically Field-Programmable Array (DPQA) Processor. In this architecture, atoms are strategically placed within Spatial Light Modulator (SLM) trap pairs, ensuring that the distance between them is smaller than $r_{\mathrm{int}}$ while maintaining an inter-pair distance larger than $r_{\mathrm{re}}$ to prevent mutual restrictions. Computation in a DFPA processor can be considered as the repetition of three major phases: (a) Loading phase: A subset of atoms undergoes a switching process to be rearranged using Acousto-Optic Deflectors (AODs), indicated by the AOD coordinates $x$ and $y$. (b + c) Shuttling phase: The trapped atoms are rearranged by readjusting the AOD coordinates. To avoid conflicts due to row crossing, the atom in the lower left corner (indicated in red) must be displaced first, allowing the other atom to occupy its designated position. In particular, for $y_2$ to reach its destination, the $y_3$ row has to be moved along as the coordinates are not allowed to cross. Subsequently, the remaining atoms, and also $y_3$, can be shuttled to their respective locations. For more complicated shuttling operations this requires sophisticated methods to find adequate AOD movements. (d) Gate phase: An entangling CZ gate can be performed on atoms within the same pair of traps. This operation can be accomplished either with a global laser beam or individually using selective beams, as discussed in \ref{['fig:capabilities']}. Phases (a) to (d) are repeated iteratively until all the required gates have been executed.
• Figure 4: Compilation and Evaluation Process Overview for the Neutral Atom Quantum Computing Platform. 1. Input/Preprocessing: The platform-independent compilation processes lead to a circuit description that includes abstract and hardware-independent gates. 2. Computational capabilities: The different computational capabilities of the NAQC platform, as elaborated in \ref{['sec:comp-capabilities']} with a short description of the constraints for the corresponding compilation subtasks of synthesis, mapping, and routing. Depending on the hardware setup, multiple capabilities, including all, can be considered. 3. Figures of merit: The compilation output is evaluated based on capability-specific proxy criteria, such as gate or shuttling operation counts. To achieve a more comprehensive comparison and evaluation of gate-based routing and shuttling, figures of merit, such as the final execution time and fidelity of the compilation result, can be computed.
• Figure 5: Long-range Interaction Analysis: In the left graph, we computed the fidelity reduction based on SWAP gate insertion and qubit idling for diverse circuits with a dimension of $n=120$ and varying interaction radii $r_{\mathrm{int}}$. The displayed curve represents the effective coherence time required to equate $\mathcal{F}_\mathrm{idle}$ and $\mathcal{F}_\mathrm{mapping}$. This signifies that, given a circuit, when $T_{\mathrm{eff}}$ surpasses (falls below) the line, the dominant fidelity reduction is caused by SWAP gates (decoherence). Larger $r_{\mathrm{int}}$ diminishes the SWAP error due to augmented connectivity, necessitating larger coherence times to balance the influence of both errors. Owing to the prolonged coherence times of the Rubidium hardware, SWAP gates stand as the prevailing source of fidelity reduction across all circuits. The right graph follows a similar procedure, modifying the restriction factor $r_{\mathrm{re}}$ while maintaining a fixed interaction radius of $r_{\mathrm{int}}=2d$, showing different behavior depending on the structure of the circuit. The error bars correspond to the standard deviation averaged over 10 iterations.

Theorems & Definitions (4)

• definition 1: Synthesis
• definition 2: Mapping
• definition 3: Scheduling
• Remark 1