PPU: Design and Implementation of a Pipelined Full Posit Processing Unit

TL;DR

This work demonstrates the design, integration, and evaluation of a Full Posit Processing Unit (FPPU) embedded in the Ibex low‑power RISC‑V core to execute posit arithmetic directly in hardware. The FPPU implements add/sub, mul, div, FMA, inversion, and binary32/posit conversions, organized in a multi‑stage pipeline with a division strategy based on Chebyshev reciprocity and Newton‑Raphson refinement, and is extended via a RISC‑V ISA to expose posit instructions. FPGA/SoC prototyping shows modest area overhead ($7 ext{\%}$ for 8‑bit posits and $15 ext{\%}$ for 16‑bit posits) and low dynamic power ($<1$ mW per 8‑bit operation at 20 MHz), achieving practical throughput and enabling native posit computation inside a RISC‑V workflow. Empirical validation using DNN benchmarks indicates minimal accuracy loss for 16‑bit posits compared with 32‑bit IEEE floats and competitive performance relative to traditional FPUs, highlighting the approach’s viability for edge AI and embedded numeric workloads. The work also proposes SIMD extensions and provides a concrete ISA/Compiler pipeline for posit operations, underscoring the benefits of modular RISC‑V customization for alternative number representations.

Abstract

By exploiting the modular RISC-V ISA this paper presents the customization of instruction set with posit\textsuperscript{\texttrademark} arithmetic instructions to provide improved numerical accuracy, well-defined behavior and increased range of representable numbers while keeping the flexibility and benefits of open-source ISA, like no licensing and royalty fee and community development. In this work we present the design, implementation and integration into the low-power Ibex RISC-V core of a full posit processing unit capable to directly implement in hardware the four arithmetic operations (add, sub, mul, div and fma), the inversion, the float-to-posit and posit-to-float conversions. We evaluate speed, power and area of this unit (that we have called Full Posit Processing Unit). The FPPU has been prototyped on Alveo and Kintex FPGAs, and its impact on the metrics of the full-RISC-V core have been evaluated, showing that we can provide real number processing capabilities to the mentioned core with an increase in area limited to $7\%$ for 8-bit posits and to $15\%$ for 16-bit posits. Finally we present tests one the use of posits for deep neural networks with different network models and datasets, showing minimal drop in accuracy when using 16-bit posits instead of 32-bit IEEE floats.

Figures (10)

• Figure 1: Bit fields of a posit$\left<32,6\right>$ data type.
• Figure 2: An example of Posit configuration with 16 bits and 2 exponent bits. The associated real value to the shown Posit is:$\textcolor{cyan}{+} 16^{\textcolor{darkamber}{0}}\times 2^{\textcolor{lightred}{0}}\times ( 1 + \textcolor{darkgreen}{512}/2048)= 1.25$.
• Figure 3: Bit-string layout of the fraction before rounding, with (G, R, S) bits highlighted.
• Figure 4: 3-stage Full PPU with control unit.
• Figure 5: Example of interaction with the FPPU.