Logical Synchrony and the bittide Mechanism

TL;DR

This paper addresses coordinating distributed computation without a system-wide clock by introducing logical synchrony, where causality and frame-based communications define a global temporal structure. It formalizes logical synchrony networks (LSNs) with edge latencies $\lambda_{ij}$ and an extended event graph, and then shows how multiclock networks—physical clocks $\theta_i$ connected by FIFO transports—realize LSNs and enforce nonnegative round-trip times through buffer-aware frequency control. A key contribution is the equivalence framework: clock relabeling shifts latencies by $c_i$ while preserving cycle round-trip invariants, and realizable multiclock networks are equivalent to perfectly synchronous systems under appropriate relabeling; this underpins the bittide mechanism’s ability to achieve synchronous-like execution without explicit global time references. The bittide mechanism uses elastic buffers and continuous frame transmission to adjust local clocks, preserve bounded FIFO occupancy, and enable cycle-accurate coordination at scale, with open-source implementations and simulators. The work forwards scalable, predictable distributed execution for workloads with strong timing regularities and provides a foundation for extending synchronous guarantees to a broader class of dynamic systems.

Abstract

We introduce logical synchrony, a framework that allows distributed computing to be coordinated as tightly as in synchronous systems without the distribution of a global clock or any reference to universal time. We develop a model of events called a logical synchrony network, in which nodes correspond to processors and every node has an associated local clock which generates the events. We construct a measure of logical latency and develop its properties. A further model, called a multiclock network, is then analyzed and shown to be a refinement of the logical synchrony network. We present the bittide mechanism as an instantiation of multiclock networks, and discuss the clock control mechanism that ensures that buffers do not overflow or underflow. Finally we give conditions under which a logical synchrony network has an equivalent synchronous realization.

Figures (9)

• Figure 1: A logical synchrony network (edges labeled with $\lambda$) and corresponding extended graph.
• Figure 2: Two equivalent logical synchrony graphs (edges labeled with $\lambda$). Relabeling the clocks using $c=(1,2,3)$ maps the left-hand graph to the right-hand one.
• Figure 3: Two non-equivalent logical synchrony graphs with no directed cycles (edges labeled with $\lambda$)
• Figure 4: Logical synchrony networks for Example \ref{['ex:longcycle']}
• Figure 5: Triangle invariant

Theorems & Definitions (32)

• Theorem 1
• Proof 1
• Theorem 2
• Proof 2
• Definition 1
• Definition 2
• Definition 3
• Theorem 3
• Proof 3
• Definition 4