SPICE Modeling of Memcomputing Logic Gates

TL;DR

This paper introduces SPICE models of memcomputing logic gates following their original definition and demonstrates the behavior of single gates as well as small self-organizing circuits.

Abstract

Memcomputing logic gates generalize the traditional Boolean logic gates for operation in the reverse direction. According to the literature, this functionality enables the efficient solution of computationally-intensive problems including factorization and NP-complete problems. To approach the deployment of memcomputing gates in hardware, this paper introduces SPICE models of memcomputing logic gates following their original definition. Using these models, we demonstrate the behavior of single gates as well as small self-organizing circuits. We also correct some inconsistencies in the prior literature. Importantly, the correct schematics of dynamic correction module is reported here for the first time. Our work makes memcomputing more accessible to those who are interested in this emerging computing technology.

Figures (6)

• Figure 1: Left panel: the universal self-organizing logic gate is composed of three dynamic correction modules (DCMs) and two resistors. Right panel: internal structure of the dynamic correction module (incorrect). Here, the resistive memories M chua76a09_memelements11_memory_materials have minimum and maximum resistances $R_{on}$ and $R_{off}$, respectively, and the resistor's resistance $R=R_{off}$. $L_{M_j}$-s and $L_R$ are voltage-controlled voltage generators. As we explain in the text, in the right panel, the polarity of all memristive elements must be reversed. Reprinted from Ref. Traversa17a.
• Figure 2: Functions (a) $f_{DCG}(x)$ and (b) $f_s\left( \mathbf{i}_{DCG},s_j\right)$ defined by Eqs. (\ref{['eq:fDCG']}) and (\ref{['eq:8']}), respectively. These graphs were obtained using parameters values from Table \ref{['tbl:params']} (Appendix A).
• Figure 3: Current-voltage curves of the memristive element subjected to a sinusoidal voltage. These curves were obtained using the SPICE model in Table \ref{['tbl:memR']} (Appendix B).
• Figure 4: Correct schematics of the dynamic correction module.
• Figure 5: Direct operation of self-organizing OR. (a) Circuit used in simulations. Here, V1 and V2 are the pulsed voltage sources, U1 is the self-organizing OR, U2 is the VCDCG, and U18 is the s-block. (b) Voltage transient signals at the terminals of self-organizing OR and voltage output of VCDCG (terminal 3 of U2). The curves were displaced for clarity.