Constructive plaquette compilation for the parity architecture

TL;DR

The paper tackles the challenge of mapping higher-order optimization problems into a parity architecture while preserving locality. It introduces a constructive, layer-by-layer rectangular plaquette compilation that represents interior qubits via a boundary map $B$ and realizes parity constraints with a plaquette space $P$, augmented by ancilla qubits as needed; the approach is grounded in GF($2$) linear algebra and proves that the final constraint space satisfies $R(C'_f)=R(C)$. Key contributions include a formal parity constraint algebra, a systematic plaquette-decomposition procedure that uses only three of four triangle orientations, a strategy for adding qubits when constraints are too long, and ancilla-minimization considerations, as well as guidance for incorporating side conditions in constrained optimization problems. The method enables efficient, parallelizable implementations on near-term hardware for both analog and digital quantum devices, and supports hardware-software co-design by providing a constructive path from high-order terms to a local plaquette layout.

Abstract

Parity compilation is the challenge of laying out the required constraints for the parity mapping in a local way. We present the first constructive compilation algorithm for the parity architecture using plaquettes for arbitrary higher-order optimization problems. This enables adiabatic protocols, where the plaquette layout can natively be implemented, as well as fully parallelized digital circuits. The algorithm builds a rectangular layout of plaquettes, where in each layer of the rectangle at least one constraint is added. The core idea is that each constraint, consisting of any qubits on the boundary of the rectangle and some new qubits, can be decomposed into plaquettes with a deterministic procedure using ancillas. We show how to pick a valid set of constraints and how this decomposition works. We further give ways to optimize the ancilla count and show how to implement optimization problems with additional constraints.

Figures (6)

• Figure 1: Example showing how the dimension of the constraint space implied by the layout increases by one after placing each constraint. Suppose that the lower plaquettes are already placed, so our matrix $P$ at this time consists of the following row vectors (we can identify bit vectors with sets) $\{a, \ell_1, \ell_2\}$, $\{b, \ell_2, \ell_5\}$, and $\{d, \ell_3, \ell_5\}$. The boundary map matrix $B$ is given by the following rows: $\{\ell_1, a, b, \ell_5\}$, $\{\ell_2, b, \ell_5\}$, and $\{\ell_3, d, \ell_5\}$. Each row of $B$ is in the rowspace of $P$. Suppose that we choose $c = \{\ell_1, \ell_3, x, y\}$ as a new constraint to implement. Since $\ell_1$ and $\ell_3$ are not on the boundary, we add corresponding rows from $B$, viz., $\{\ell_1, a, b, \ell_5\}$ and $\{\ell_3, d, \ell_5\}$ to $c$ to get $c' = \{a, b, d, x, y\}$, which is implemented as shown in the figure above. If you add all the colored plaquettes, you end up with $c'$ (and if you add $\{\ell_1, a, b, \ell_5\}$ and $\{\ell_3, d, \ell_5\}$ to $c'$, you get back $c$, which is the constraint we wanted to implement). Notice that even though we added three plaquettes, we also added two ancillas $\alpha_1$ and $\alpha_2$, which means effectively that the dimension of implied constraint space increased by one, and we are one step closer to completing the layout.
• Figure 2: Three examples of constraints consisting of some boundary qubits in grey and some new qubits in white. The unlabeled qubits are not part of the constraints as they are in exactly two plaquettes. The new (white) unlabelled qubits are ancillas that can be eliminated using the constraint algebra discussed before (in each figure the number of plaquettes is exactly one larger than the number of white unlabeled qubits). (a) A 5-qubit constraint involving the boundary qubits $a$, $b$ and $c$ and two new qubits $x$ and $y$. (b) A 3-qubit constraint involving the boundary qubits $a$, $b$ and $c$ that are not directly next to each other. (c) A 3-qubit constraint involving the boundary qubits $a$, $b$ and $c$ such that the first two qubits are directly next to each other. To be able to draw this constraint a fixed ancilla qubit $+$ is required, which is not a degree of freedom.
• Figure 3: Example of a 4-qubit constraint involving the qubits $a$, $b$, $c$ and $d$. In this case the corner qubit $c$ is in three plaquettes, so it will be part of the constraint, whereas the unlabeled qubits are in exactly two constraints. If the corner qubit $c$ was not part of the constraint, one of the two squares that $c$ is in would have to be a triangle, leaving $c$ in only two plaquettes. In this fashion, a constraint with up to three unplaced qubits can be added, one qubit above $a$, one qubit diagonally outward from $c$ and one qubit to the right of $d$, by turning the respective triangles into squares.
• Figure 4: A compilation of a problem with $5$ interactions and $5$ logical qubits, which requires a single parity constraint between all $5$ qubits. The black line shows the separation between the first and second layer. The $5$ white qubits corresponds to Hamiltonian interactions (e.g., $12$ corresponds to the interaction $\sigma_z^{(1)}\sigma_z^{(2)}$) and the grey qubit to an ancilla. The white constraint is placed first and the ancilla is necessary to break up the long constraint into shorter constraints. The red constraint then finishes the layout.
• Figure 5: Two different compilations of a problem represented by a Hamiltonian with $25$ interactions and $10$ logical qubits. The black grid shows the different layers that build up the rectangle. The $25$ white qubits corresponds to Hamiltonian interactions (e.g., $78$ corresponds to the interaction $\sigma_z^{(7)}\sigma_z^{(8)}$) and the grey qubits to ancillas. The plaquette labels number the $16$ required constraints, where some constraints require more than one plaquette and neighboring constraints are plotted in different colors. In the top figure, there are also two grey plaquettes that are not directly helping implement a constraint, but are necessary for bringing qubit information to the boundary. Unnecessary grey plaquettes are removed from the outer layers of the layout.