A Cryogenic Memristive Neural Decoder for Fault-tolerant Quantum Error Correction

TL;DR

This work design and analyze a neural decoder based on an in-memory computation (IMC) architecture, where crossbar arrays of resistive memory devices are employed to both store the synaptic weights of the neural decoder and perform analog matrix-vector multiplications, and develops hardware-aware re-training methods to mitigate the fidelity loss.

Abstract

Neural decoders for quantum error correction (QEC) rely on neural networks to classify syndromes extracted from error correction codes and find appropriate recovery operators to protect logical information against errors. Its ability to adapt to hardware noise and long-term drifts make neural decoders a promising candidate for inclusion in a fault-tolerant quantum architecture. However, given their limited scalability, it is prudent that small-scale (local) neural decoders are treated as first stages of multi-stage decoding schemes for fault-tolerant quantum computers with millions of qubits. In this case, minimizing the decoding time to match the stabilization measurements frequency and a tight co-integration with the QPUs is highly desired. Cryogenic realizations of neural decoders can not only improve the performance of higher stage decoders, but they can minimize communication delays, and alleviate wiring bottlenecks. In this work, we design and analyze a neural decoder based on an in-memory computation (IMC) architecture, where crossbar arrays of resistive memory devices are employed to both store the synaptic weights of the neural decoder and perform analog matrix-vector multiplications. In simulations supported by experimental measurements, we investigate the impact of TiOx-based memristive devices' non-idealities on decoding fidelity. We develop hardware-aware re-training methods to mitigate the fidelity loss, restoring the ideal decoder's pseudo-threshold for the distance-3 surface code. This work provides a pathway to scalable, fast, and low-power cryogenic IMC hardware for integrated fault-tolerant QEC.

Figures (9)

• Figure 1: Decoding process. In *QEC, syndrome extraction rounds are performed cyclically to protect an encoded quantum state $\ket{\psi}_L$ from logical errors. Typically, the $X$ and $Z$ stabilizers' syndromes are processed separately but simultaneously by two independent decoding modules. The syndrome measurement outcomes are fed to the decoder modules, which analyze them to produce a decision output $(r_X,r_Z)$. This decision output is used to construct the recovery operation $Z_{L}^{r_Z}X_{L}^{r_X}$. Between the end of the last QEC round at $t_r$ and the application of the recovery operation at $t_{r+i}$, idling errors can affect the qubits, and they will not be taken into account by the decoding algorithm. The encoded state just prior to the application of recovery operations is therefore $X_{L}^{\epsilon_X}Z_{L}^{\epsilon_Z}\ket {\psi}_L$, where $\epsilon_{x,z}$ represents the cumulative effect of the errors that occur during the QEC rounds and the idling time $t_{\textrm{delay}}$. Following the application of the recovery operation (here assumed to be ideal for simplicity), the final encoded logical quantum state is $X_{L}^{\epsilon_X+r_X}Z_{L}^{\epsilon_Z+r_Z}\ket{\psi}_L$. Here, the example decoder is based on a *RNN. Each new syndrome is used as the input to the RNN and the hidden state $\vec{h_i}$ is passed to the subsequent recurrence. At the end of the QEC process, the output state $\vec{l_r}$ is passed to an evaluation module *EV (the fully connected output layer in the case of RNN) to provide the final binary output of the decoder. On the right-hand side of the figure, the standard folded representation of this RNN is illustrated. A more detailed schematic architecture of this RNN decoder is depicted in Fig. \ref{['fig:RNN']}.
• Figure 2: Surface code and stabilizer measurements. (a) Distance-3 rotated surface code, also called surface-17. Data qubits 1.0 to 9.0 are identified by circles filled in white, and syndrome qubits are identified by circles filled in black. Each syndrome qubit resides on a "plaquette" corresponding to a specific stabilizer measurement $S$. The sequence of operations realizing an $X$ stabilizer (pink plaquette) and a $Z$ stabilizer (green plaquette) are shown in (b) and (c). In this example, a logical operator $X_L$ ($Z_L$) can be realized by applying a chain of physical $X$ ($Z$) operators on data qubits between the top (left) and bottom (right) edge of the grid. (b) Sequence of circuit operations between a syndrome qubit (circle filled in black, the top qubit in the circuit) and its neighbouring data qubits, $e$, $f$, $g$, and $h$, realizing the stabilizer measurement $X_eX_fX_gX_h$. It consists of syndrome qubit initialization, Hadamard gates ($H$), CNOT gates, a projective measurement along the z-axis ($M_Z$), and a reset ($R$) to the $\ket{0}$ state, regardless of the measured outcome. (c) Sequence of circuit operations between a syndrome qubit and its neighbouring data qubits, $a$, $b$, $c$, and $d$, realizing the stabilizer measurement $Z_aZ_bZ_cZ_d$. It consists of syndrome qubit initialization, CNOT gates, a projective measurement along the z-axis ($M_Z$), and a reset ($R$) to the $\ket{0}$ state, regardless of the measured outcome. The black rectangles represent idling of the data qubits, which is important for simulation of the circuits. More details on the exact procedure used for the simulation of these parity-check circuits is provided in Supplementary Information Note \ref{['sec:note-quantum']}.
• Figure 3: Recurrent neural network decoder architecture and corresponding memristive decoder circuit.*QEC is handled as a sequential classification problem. (a) Error correction rounds performed by measuring stabilizer operators on the lattice of physical qubits. Ancilla qubits (the circles filled in red or black representing an error or no error being detected, respectively) measure the bit-flip $X$ (phase-flip $Z$) stabilizers $\hat{S}_{\{1-4\}}^X$ ($\hat{S}_{\{1-4\}}^Z$). Measured eigenvalues of ancillas are mapped to classical bits to build the syndromes $s^{X}$ and $s^{Z}$, which serve as inputs to the neural decoder. Here, we consider only the $s^{X}$ syndromes, obtained at times $t=1, 2, 3, 4$. (b) Recurrent neural network decoder architecture for the distance-3 surface code. It comprises a recurrent layer and an output layer. Bias is also applied to both layers. The syndrome at $t=1$ is the initial input along with the initialized hidden state $\vec{h_0}$. The output of the recurrent layer is routed back to be used as new input to the internal state nodes, as a new syndrome($t=2$) is provided to the input nodes. This is repeated until the last QEC round at time $t=n$ (here, $n=4$), when the output of the recurrent layer is forwarded to the output layer, where the value of the single output neuron is compared to a threshold value to produce a binary classification. (c) Memristive decoder circuit. It is composed of two arrays of memristors. The first is applied recursively (recurrent array) until $t=n$, and the second acts as the classifier (output array). Input syndromes are converted from the digital domain to the analog domain by digital-to-analog converters so that the memristive crossbar can perform the analog matrix--vector multiplication. The memristor conductances are programmed according to the digitally trained weights of the equivalent neural network decoder. Differential amplifiers subtract the outputs from each pair of memristor columns to obtain the resulting node's value. This signal is forwarded to the activation function array (green rectangle), where an analog-to-digital conversion is performed to apply a digital ReLU activation function. The signal is converted back to the analog domain before being routed back to the recurrence input ports or sent to the output array. Finally, the value of the output array is passed through a comparator to produce a binary classification. An additional memristor row in each array allows the application of a bias signal. (d) Recovery operation. To conclude the QEC process, a recovery operation is applied to the data qubits according to the classification provided by the decoder. The identity is applied in the case where no logical error has been detected (output 0.0), and the $Z_L$ operator is applied (circles filled in green) if a logical error has been detected (output 1.0).
• Figure 4: Programming variability characterizations of TiO$_\textrm{x}$-based resistive memory and its impact on the neural decoder. (a) Pulse programming of 11.0 conductance states of a TiO$_\textrm{x}$-based resistive memory device. Positive voltage pulses induce a conductance increase (labeled "SET pulse") due to the growth of the conductive filament inside the TiO$_\textrm{x}$ layer between the electrodes. Negative voltage pulses are employed to decrease the conductance ("RESET pulse") due to the rupture of the conductive filament. The dotted black lines denote the target conductance ("$G_\mathrm{TARGET}$"), whereas the red dots denote the programmed conductance ("$G_\mathrm{PROG}$") values upon convergence of the closed-loop read--write--verify algorithm. The inset is a zoom-in on the readout of the 100 state within the allowed error of 1. (b) Programming variability model based on the programming standard deviations of multiple conductance states. The multilevel programming cycle shown in (a) is conducted 10.0 times in a double sweep for 10.0 devices. For each conductance state, the standard deviation of the distribution of programmed values is extracted to fit a programming variability model, except for the *HCS and the *LCS. (c) Decoding fidelity of a distance-3 surface code for a typical physical fault rate of $10^{-2}$ using a trained *RNN, as a function programming variability of the weights, represented as a factor of the polynomial fit used in (b). The error bands represent the 95 confidence interval over 10.0 random seeds. The performance of the RNN remains close to the digital baseline before the noise standard deviation reaches a factor of $\sim$10.0 times higher than the experimental value, after which the fidelity drops significantly.
• Figure 5: Baselines and re-training methods for the memristive neural decoder. (a) Schematic representation of the methods used to train the *RNN decoder. The fidelity of the digital baseline is tested immediately after classical training. The *HWA and *DS *MND methods benefit from a re-training step after being converted to a memristor-based model with the IBM Analog Hardware Acceleration KitRasch_2021, whereas the MND baseline training method is converted and tested without any re-training. (b) *LFR after decoding as a function of the *PFR. The intersection between the line "LFR = PFR" and decoder performances represent the breakeven points (i.e., the pseudo-threshold values) of the corresponding neural decoders. (c) Logical fidelity percentage of the decoder at a PFR of $10^{-2}$, for the baselines and the re-trained decoders, as a function of the percentage of stuck-at fault devices. For the HWA-MND, the stuck-at fault devices define the dropconnect rate used during re-training. (d) Logical fidelity percentage of the decoder at a PFR of $10^{-2}$ for the baselines and the re-trained decoders. For the results presented in (b) and (d), the rate of stuck-at fault devices is set at the expected fabrication yield of 10. For the results presented in (b), (c), and (d), the digital baseline fidelity is obtained with an equivalent neural decoder. The error bars and shaded regions represent the 95 confidence interval over 10.0 random seeds.