Increasing the Measured Effective Quantum Volume with Zero Noise Extrapolation

TL;DR

This work addresses how error mitigation can alter a standard quantum volume benchmark by introducing effective quantum volume (effective_QV) that uses zero-noise extrapolation (ZNE). It outlines a complete workflow combining circuit generation, unitary folding (global and local), dynamical decoupling, and hardware execution with linear extrapolation to the zero-noise limit. The key finding is that effective_QV can exceed vendor-measured QV on multiple IBM devices, though extrapolation can fail when decoherence erases signal, underscoring both the potential and limits of near-term quantum error mitigation. The study demonstrates the practical impact of ZNE on benchmark scalability and motivates further exploration of mitigation strategies within full-stack quantum benchmarking.

Abstract

Quantum Volume is a full-stack benchmark for near-term quantum computers. It quantifies the largest size of a square circuit which can be executed on the target device with reasonable fidelity. Error mitigation is a set of techniques intended to remove the effects of noise present in the computation of noisy quantum computers when computing an expectation value of interest. Effective quantum volume is a proposed metric that applies error mitigation to the quantum volume protocol in order to evaluate the effectiveness not only of the target device but also of the error mitigation algorithm. Digital Zero-Noise Extrapolation (ZNE) is an error mitigation technique that estimates the noiseless expectation value using circuit folding to amplify errors by known scale factors and extrapolating to the zero-noise limit. Here we demonstrate that ZNE, with global and local unitary folding with fractional scale factors, in conjunction with dynamical decoupling, can increase the effective quantum volume over the vendor-measured quantum volume. Specifically, we measure the effective quantum volume of four IBM Quantum superconducting processor units, obtaining values that are larger than the vendor-measured quantum volume on each device. This is the first such increase reported.

Figures (13)

• Figure 1: Circuit drawing for a logical QV circuit acting on $n=7$ qubits, where each layer $d=1,\ldots,d=7$ consists of a random permutation of the qubit labels followed by $n' = 3 =\lfloor \tfrac{7}{2} \rfloor$ random SU(4) gates acting on consecutive pairs of (the permuted) qubits. This figure was realized using Quantikz quantikz.
• Figure 2: High-level workflow of the methodology for estimating the effective quantum volume with zero-noise extrapolation. First, the raw uncomputed QV circuits are initially defined with arbitrary connectivity and basis gates U3 and CX. Second, the Qiskit transpiler is run on the target hardware subgraph with optimization_level=3. Third, the QASM circuits are folded via either global or local folding with Mitiq. Fourth, the native gateset is adapted to RZ, CX, SX, and X using the Qiskit transpiler with optimization_level=0. Fifth, an optional step, X-X digital dynamical decoupling is applied.
• Figure 3: All subgraph isomorphisms for $n=6$ on the heavy-hex connectivity.
• Figure 4: All subgraph isomorphisms for $n=7$ on heavy hex connectivity.
• Figure 5: Three Qiskit Qiskit timeline diagrams of a single $n=4$ Quantum Volume circuit compiled to a subgraph of a heavy hex graph, specifically qubits 15, 18, 17, 21 of ibm_hanoi. Top diagram shows the compiled QV circuit, with optimizations applied. The middle and bottom circuit diagrams are the same compiled circuit with a digital ZNE circuit folding scale factor of $\lambda=2$ having been applied. Local CNOT circuit folding is used for the middle plot, and global circuit folding is used in the bottom plot. Digital dynamical decoupling sequences of X-X Pauli gates are inserted into all of the the circuits, and the all circuits are scheduled using the ALAP circuit scheduler. The RZ gates are virtual gates McKay_2017, and are represented here by circular black arrow markers. The X gates are shown as green vertical lines, which are very thin because the single qubit gate operations take a small amount of time. Similarly, the short duration single qubit SX gate is represented as vertical red lines. The CX (e.g. CNOT) gates are drawn as vertical blue connections between adjacent qubits in the hardware graph. The dark grey segments at the end of each qubit line denote the measurement of the $4$ qubits. The uncompiled QV circuit contained 24 CX gates, which was then turned into 18 CX gates when optimized using the Qiskit transpiler and adapted to the heavy hex graph structure (shown in the top circuit diagram). ZNE global folding (bottom) with $\lambda=2$ generated a circuit invariant with $36$CX gates, and local random folding (middle) with $\lambda=2$ generated a circuit with $42$CX gates.