ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI

TL;DR

The paper addresses the rising embodied carbon emissions in semiconductor design by focusing on chiplet-based heterogeneous integration (HI) as a path to sustainable VLSI. It introduces ECO-CHIP, an architectural-level carbon-footprint estimator that explicitly accounts for packaging overheads, yields, area scaling, and design and operational energy across HI systems. The framework demonstrates potential embodied CFP reductions up to about 70% relative to monolithic designs and provides insights into how technology-node mixing, packaging choices, and chiplet reuse can drive greener designs; it also integrates with other chiplet tools and is open-sourced. By enabling design-space exploration that couples carbon metrics with performance, ECO-CHIP offers a practical pathway to integrate sustainability into HI-enabled product development.

Abstract

Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to an increase in embodied emissions, encompassing carbon emissions arising from design, manufacturing, packaging, and other infrastructural activities. While existing research has developed tools to analyze embodied carbon at the computer architecture level for traditional monolithic systems, these tools do not apply to near-mainstream heterogeneous integration (HI) technologies. HI systems offer significant potential for sustainable computing by minimizing carbon emissions through two key strategies: ``reducing" computation by reusing pre-designed chiplet IP blocks and adopting hierarchical approaches to system design. The reuse of chiplets across multiple designs, even spanning multiple generations of integrated circuits (ICs), can substantially reduce embodied carbon emissions throughout the operational lifespan. This paper introduces a carbon analysis tool specifically designed to assess the potential of HI systems in facilitating greener VLSI system design and manufacturing approaches. The tool takes into account scaling, chiplet and packaging yields, design complexity, and even carbon overheads associated with advanced packaging techniques employed in heterogeneous systems. Experimental results demonstrate that HI can achieve a reduction of embodied carbon emissions up to 70\% compared to traditional large monolithic systems. These findings suggest that HI can pave the way for sustainable computing practices, contributing to a more environmentally conscious semiconductor industry.

Figures (15)

• Figure 1: Embodied and operational CFP sources in the VLSI supply chain imec-wp.
• Figure 2: (a) Embodied CFP versus area of the chip. (b) Comparison of manufacturing CFP of the large monolithic NVIDIA GA102 GPU and a 4-chiplet-based architecture of the GPU.
• Figure 3: (a) Dies on a wafer highlighting the green and white regions of the wafer that are wasted. (b) Comparison of the manufacturing CFP with and without analyzing wastage around wafer periphery for GA102 GPU monolithic and 4-chiplet-based architecture on a 450mm wafer.
• Figure 4: Packaging architectures: (a) RDL fanout, (b) thin-film and silicon bridge architecture (Intel's EMIB, TSMC's LSI), (c) 2.5D integration with active or passive interposers and (4) 3D stacking with TSVs and microbumps.
• Figure 5: ECO-CHIP framework highlighting inputs and the models developed to output embodied and operational carbon. The embodied CFP estimation accounts for the CFP from packaging (red), manufacturing (blue), and design (yellow). The operational CFP (green) is estimated from power models.