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Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection

Shan Shen, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu

TL;DR

Ultra8T addresses the challenge of sustaining SRAM operation in sub-/near-threshold regimes for energy-constrained IoT systems by introducing a leakage-detection strategy that defines a safe bitline-sensing window without additional hardware. The approach maps leakage currents to a digital timing cue via a SOSA-based sense amplifier and a digitized timing module, enabling robust reads from $V_{DD}$ as low as $0.25$ V while preserving speed. Key contributions include a leakage model and safety-window bounds under PVT, a low-offset SOSA, and a replica-column-based timing scheme for TVT tracking, validated in a 256×64 array in 28 nm. The results show a read delay of $1.11$ μs at $0.25$ V and a minimum energy of $1.69$ pJ at $0.4$ V, highlighting significant energy efficiency gains for sub-threshold SRAM in IoT SoCs.

Abstract

In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage (VDDMIN). In this work, we propose an Ultra8T SRAM to aggressively reduce VDDMIN by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256x64 array in 28nm CMOS technology. Post-simulations show successful read operation at 0.25V with 1.11μs read delay, and the minimum energy required is 1.69pJ at 0.4V.

Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection

TL;DR

Ultra8T addresses the challenge of sustaining SRAM operation in sub-/near-threshold regimes for energy-constrained IoT systems by introducing a leakage-detection strategy that defines a safe bitline-sensing window without additional hardware. The approach maps leakage currents to a digital timing cue via a SOSA-based sense amplifier and a digitized timing module, enabling robust reads from as low as V while preserving speed. Key contributions include a leakage model and safety-window bounds under PVT, a low-offset SOSA, and a replica-column-based timing scheme for TVT tracking, validated in a 256×64 array in 28 nm. The results show a read delay of μs at V and a minimum energy of pJ at V, highlighting significant energy efficiency gains for sub-threshold SRAM in IoT SoCs.

Abstract

In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage (VDDMIN). In this work, we propose an Ultra8T SRAM to aggressively reduce VDDMIN by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256x64 array in 28nm CMOS technology. Post-simulations show successful read operation at 0.25V with 1.11μs read delay, and the minimum energy required is 1.69pJ at 0.4V.
Paper Structure (19 sections, 20 equations, 16 figures, 2 tables)

This paper contains 19 sections, 20 equations, 16 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Backgrounds
  3. 8T SRAM Read Access
  4. Recent Works on Ultra-Low-Voltage SRAMs
  5. Analysis of Leakage and Sensing Window
  6. Modeling Sensing Window without Variations
  7. Combining with PVT Variations
  8. Design of Ultra8T SRAM
  9. The Principle
  10. Overall Structure
  11. SOSA
  12. Digitized Timing
  13. Evaluation
  14. Normal Read Mode
  15. Test Mode
  16. ...and 4 more sections

Figures (16)

  • Figure 1: Schematic of 8T SRAM column.
  • Figure 2: The worst-case for reading ‘1’ and ‘0’ in a 256-rowed column at (a) 0.45V and (b) 0.5V VDD.
  • Figure 3: (a)Mean of $i_l$ v.s. column-depth $N$ of SRAM at 0.25V, 25C. (b) Mean of $i_l$ v.s. VDD with different $R_{01}$. (c) $i_l$ v.s. temperature with different VDD.
  • Figure 4: (a) $\frac{T_{leak}}{T_{r0}}$ v.s. VDD with different temperatures. (b) $\frac{T_{leak}}{T_{r0}}$ v.s. temperature with different voltages.
  • Figure 5: Mean and std of $i_{r0}$ and $i_l$ v.s. VDD.
  • ...and 11 more figures