Single-Step Parity Check Gate Set for Quantum Error Correction

TL;DR

The paper tackles the challenge of achieving practical fault-tolerance in quantum computing by redefining the fundamental parity-check operations used in QEC. It introduces the single-step parity check (SSPC) gate set, native to QEC tasks, and develops a formal framework that maps experimental process matrices to QEC Pauli error models, enabling direct linkage to fault-tolerance thresholds. Applying this to the Honeycomb code and a silicon-spin system, the authors demonstrate that SSPC gates can significantly reduce error accumulation and potentially raise practical thresholds compared to decomposed, universal-gate implementations. This work provides a concrete workflow for hardware engineers to redesign gate libraries around QEC primitives, with tangible demonstrations using GRAPE-optimized SSPC pulses in a 2P1e silicon device, offering a pathway toward scalable, fault-tolerant quantum computation.

Abstract

A key requirement for an effective Quantum Error Correction (QEC) scheme is that the physical qubits have error rates below a certain threshold. The value of this threshold depends on the details of the specific QEC scheme, and its hardware-level implementation. This is especially important with parity-check circuits, which are the fundamental building blocks of QEC codes. The standard way of constructing the parity check circuit is using a universal set of gates, namely sequential CNOT gates, single-qubit rotations and measurements. We exploit the insight that a QEC code does not require universal logic gates, but can be simplified to perform the sole task of error detection and correction. By building gates that are fundamental to QEC, we can boost the threshold and ease the experimental demands on the physical hardware. We present a rigorous formalism for constructing and verifying the error behavior of these gates, linking the physical measurement of a process matrix to the abstract error models commonly used in QEC analysis. This allows experimentalists to directly map the gates used in their systems to thresholds derived for a broad-class of QEC codes. We give an example of these new constructions using the model system of two nuclear spins, coupled to an electron spin, showing the potential benefits of redesigning fundamental gate sets using QEC primitives, rather than traditional gate sets reliant on simple single and two-qubit gates.

Figures (16)

• Figure 1: Hierarchy for scalability: The threshold is a fundamental component in practical quantum error correction (QEC), serving as a critical benchmark to gauge QEC scheme efficacy in rectifying quantum system errors. Attaining a sufficiently high threshold is essential for feasible QEC implementation; without it, practicality is compromised or rendered impossible. Crossing the threshold marks the point at which QEC becomes effective, enabling Fault Tolerant Quantum Computation (FTQC). The FTQC implementation is vital for realizing accurate and reliable quantum applications. Thus, a high threshold ensures not only QEC feasibility but also unlocks the potential for FTQC.
• Figure 2: XX and XXXX parity check measurements using $M_{pp1}$. a) a two-body parity check circuit. The circuit outputs the parity information of the two qubits in the $X$ basis by sequentially applying CNOT gates between the ancilla and q1 and q2, followed by measuring the ancilla -$M_{pp1}$-. b) a four-body parity check circuit. The circuit outputs the parity information of the four qubits in the $X$ basis by sequentially applying CNOT gates between the ancilla and four qubits, followed by measuring the ancilla -$M_{pp1}$-.
• Figure 3: Honeycomb code a) General structure of the Honeycomb code. Black dots represents physical qubits. Multiplying blue and red edges yields the green face (6 body Y stabilizer). Multiplying blue and green edges yields the red face (6 body X stabilizer). Multiplying red and green edges yields the blue face (6 body Z stabilizer). b) Measurements for the Honeycomb Code. Honeycomb code requires two body parity check: XX, YY and ZZ c) Equivalent circuits for XX, YY, and ZZ parity measurement using the traditional method: 1- and 2-qubit gates, plus $M_{pp1}$.
• Figure 4: Analysis of the XX parity check circuit in terms of QEC. The circuit depth is 6 (6 steps to calculate in the widget). Commencing with $\rho_i$, each step the value of having no error in the channel ($P_I$) decrease since the errors accumulate to the next step of the circuit
• Figure 5: Single-step Parity Check Gate for XX. a) $M_{pp2}$ with current resources. The gates inside the dashed rectangle represent the 1- and 2-qubit operations normally used to build the XX$M_{pp(2)}$. b) A natural $M_{pp(2)}$. The noise model incorporates Pauli errors from the set defined in Equation Equation \ref{['eq:Mpp2']}. c) Natural $M_{pp(2)}$ as a widget: new unitary $U_{XX}$ and 1-qubit measurement operator.