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RIP Linked List

Benoît Sonntag, Dominique Colnet

TL;DR

RIP Linked List investigates whether traditional linked lists remain practical in the era of large RAM and cache hierarchies. It compares NoCacheList, LinkedList, and SingleList against array-based structures (ArrayList, ArrayRing, ArrayBlock) via Stroustrup and Fairbench benchmarks and introduces ArrayBlock as a cache-friendly, multi-level array design. The study shows that array-based representations generally outperform linked lists, especially when memory caches and block-based strategies are exploited; with a larger N, ArrayBlock often offers the best overall performance, while linked lists benefit mainly from internal index caches. The work highlights practical guidance for library designers to provide multiple data-structure representations and demonstrates how modern hardware favors contiguous layouts for speed.

Abstract

Linked lists have long served as a valuable teaching tool in programming. However, the question arises: Are they truly practical for everyday program use? In most cases, it appears that array-based data structures offer distinct advantages, particularly in terms of memory efficiency and,more importantly, execution speed. While it's relatively straightforward to calculate the complexity of operations, gauging actual execution efficiency remains a challenge. This paper addresses this question by introducing a new benchmark. Our study compares various linked list implementations with several array-based alternatives. We also demonstrate the ease of incorporating memory caching for linked lists, enhancing their performance. Additionally, we introduce a new array-based data structure designed to excel in a wide range of operations.

RIP Linked List

TL;DR

RIP Linked List investigates whether traditional linked lists remain practical in the era of large RAM and cache hierarchies. It compares NoCacheList, LinkedList, and SingleList against array-based structures (ArrayList, ArrayRing, ArrayBlock) via Stroustrup and Fairbench benchmarks and introduces ArrayBlock as a cache-friendly, multi-level array design. The study shows that array-based representations generally outperform linked lists, especially when memory caches and block-based strategies are exploited; with a larger N, ArrayBlock often offers the best overall performance, while linked lists benefit mainly from internal index caches. The work highlights practical guidance for library designers to provide multiple data-structure representations and demonstrates how modern hardware favors contiguous layouts for speed.

Abstract

Linked lists have long served as a valuable teaching tool in programming. However, the question arises: Are they truly practical for everyday program use? In most cases, it appears that array-based data structures offer distinct advantages, particularly in terms of memory efficiency and,more importantly, execution speed. While it's relatively straightforward to calculate the complexity of operations, gauging actual execution efficiency remains a challenge. This paper addresses this question by introducing a new benchmark. Our study compares various linked list implementations with several array-based alternatives. We also demonstrate the ease of incorporating memory caching for linked lists, enhancing their performance. Additionally, we introduce a new array-based data structure designed to excel in a wide range of operations.
Paper Structure (8 sections, 16 figures, 4 algorithms)

This paper contains 8 sections, 16 figures, 4 algorithms.

Table of Contents

  1. Introduction
  2. Linked-lists Representations
  3. Array-based representations
  4. The Bjarne Stroustrup benchmark
  5. Fairbench: just fine for linked lists
  6. Endgame: Add First or Remove Last
  7. Benchmarking Methodology
  8. Conclusion

Figures (16)

  • Figure 1: A doubly linked list with a memory cache for size, containing 4 data items. The head pointer is stored in first link, and the tail pointer in last link.
  • Figure 2: Same layout as the one of Fig. \ref{['NoCacheList']}, but with an extra cache of the last visited index (cache link and cache index).
  • Figure 3: One-way linked list with memory cache for the size and the last visited index (cache link and cache index).
  • Figure 4: Used area on the left and supply area on the right. Same indexing in the native array and in the user interface.
  • Figure 5: The storage area is used in a circular fashion, from left to right. The variable lower is used to locate the internal index of data #0.
  • ...and 11 more figures