Lower-depth programmable linear optical processors
Rui Tang, Ryota Tanomura, Takuo Tanemura, Yoshiaki Nakano
TL;DR
The paper addresses the high phase-shifter depth of traditional MZI-based programmable LOPs by introducing a MPLC-based architecture that uses $N$ input/output ports from an $N'\times N'$ universal multiport interferometer with $N' \ge 2N$. The core idea embeds the standard $S = U\Sigma V$ decomposition into a larger unitary that can be realized with a reduced circuit depth, achieving $N+2$ phase shifter stages for dense matrices and $N+3$ for sparse ones in numerical tests. Experiments show comparable performance across MMI and MDC couplers and demonstrate robustness to phase quantization relative to conventional MZI meshes. Overall, this approach enables compact, low-loss, and energy-efficient programmable LOPs with potential impact on on-chip optical computing and information processing.
Abstract
Programmable linear optical processors (LOPs) can have widespread applications in computing and information processing due to their capabilities to implement reconfigurable on-chip linear transformations. A conventional LOP that uses a mesh of Mach-Zehnder interferometers (MZIs) requires $2N+3$ stages of phase shifters for $N \times N$ matrices. However, it is beneficial to reduce the number of phase shifter stages to realize a more compact and lower-loss LOP, especially when long and lossy electro-optic phase shifters are used. In this work, we propose a novel structure for LOPs that can implement arbitrary matrices as long as they can be realized by previous MZI-based schemes. Through numerical analysis, we further show that the number of phase shifter stages in the proposed structure can be reduced to $N+2$ and $N+3$ for a large number of random dense matrices and sparse matrices, respectively. This work contributes to the realization of compact, low-loss, and energy-efficient programmable LOPs.
