Introducing Reduced-Width QNNs, an AI-inspired Ansatz Design Pattern

TL;DR

The paper addresses the challenge of training-efficient, noise-robust quantum neural networks (QNNs) by introducing a reduced-width, gate-pruned ansatz inspired by dropout regularization. It evaluates two pruning strategies within a variational quantum eigensolver (VQE) framework for the Max-Cut problem, demonstrating up to approximately a 5x speedup in training time while maintaining comparable solution quality in noisy simulations. The approach leverages layerwise training and a progressive pruning scheme to balance expressibility and trainability in near-term quantum devices. This reduced-width design offers a scalable, hardware-aware design pattern for quantum optimization and motivates broader testing across base architectures and larger problem instances.

Abstract

Variational Quantum Algorithms are one of the most promising candidates to yield the first industrially relevant quantum advantage. Being capable of arbitrary function approximation, they are often referred to as Quantum Neural Networks (QNNs) when being used in analog settings as classical Artificial Neural Networks (ANNs). Similar to the early stages of classical machine learning, known schemes for efficient architectures of these networks are scarce. Exploring beyond existing design patterns, we propose a reduced-width circuit ansatz design, which is motivated by recent results gained in the analysis of dropout regularization in QNNs. More precisely, this exploits the insight, that the gates of overparameterized QNNs can be pruned substantially until their expressibility decreases. The results of our case study show, that the proposed design pattern can significantly reduce training time while maintaining the same result quality as the standard "full-width" design in the presence of noise.

Figures (6)

• Figure 1: Example network architecture of the encoder in an autoencoder.
• Figure 2: The full-width design in which gates are applied over the full width of the circuit throughout all layers. The circuit is displayed with four layers, in-line with its configuration in our evaluation.
• Figure 3: The random-width design in which a specific number of gates are deleted from the full-width design at random positions. The number of gates removed gates equals the number of removed gates in the reducing-width circuit. The circuit is displayed with four layers, in-line with its configuration in our evaluation.
• Figure 4: The reducing-width design in which the width is reduced from layer to layer by a magnitude of two. With this design approach, we prune the circuit to a version which uses much fewer gates. The circuit is displayed with four layers, in-line with its configuration in our evaluation.
• Figure 5: Average execution time necessary to train each layer for the different circuit design schemes.