ChipGPT: How far are we from natural language hardware design

TL;DR

ChipGPT investigates automatically generating hardware logic designs from natural-language specifications using a four-stage zero-code framework that does not require retraining of LLMs. It introduces a Prompt Manager to craft structured prompts, an Output Manager to correct and optimize generated Verilog, and an Enumerative Search to select designs under target metrics, enabling end-to-end chip design from NL specifications. The evaluation demonstrates that ChipGPT improves programmability over prior methods and ChatGPT, and achieves significant PPA reductions on complex workloads, with minimal human intervention. The work highlights the feasibility and practical potential of natural-language interfaces to EDA frontends.

Abstract

As large language models (LLMs) like ChatGPT exhibited unprecedented machine intelligence, it also shows great performance in assisting hardware engineers to realize higher-efficiency logic design via natural language interaction. To estimate the potential of the hardware design process assisted by LLMs, this work attempts to demonstrate an automated design environment that explores LLMs to generate hardware logic designs from natural language specifications. To realize a more accessible and efficient chip development flow, we present a scalable four-stage zero-code logic design framework based on LLMs without retraining or finetuning. At first, the demo, ChipGPT, begins by generating prompts for the LLM, which then produces initial Verilog programs. Second, an output manager corrects and optimizes these programs before collecting them into the final design space. Eventually, ChipGPT will search through this space to select the optimal design under the target metrics. The evaluation sheds some light on whether LLMs can generate correct and complete hardware logic designs described by natural language for some specifications. It is shown that ChipGPT improves programmability, and controllability, and shows broader design optimization space compared to prior work and native LLMs alone.

Figures (14)

• Figure 1: Integration of our ChipGPT framework to chip design flow
• Figure 2: Ideal Agile method productivity
• Figure 3: ChipGPT productivity improvement
• Figure 4: ChipGPT design space exploration
• Figure 5: Productivity Measurement of Agile Chip Design Method