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Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

Jason Blocklove, Siddharth Garg, Ramesh Karri, Hammond Pearce

TL;DR

The paper addresses the challenge of translating natural-language hardware specifications into HDL, proposing that conversational LLMs could serve as design assistants rather than full replacements for engineers. Through a case study with ChatGPT-4, the authors co-design an $8$-bit accumulator-based microprocessor and achieve a tapeout with AI-written HDL, highlighting both the capabilities and the need for human intervention in specification and verification. Key contributions include the first hardware design study using conversational LLMs, an end-to-end workflow, and open data on logs and tooling, along with actionable recommendations for practitioners. The work demonstrates that conversational LLMs can accelerate design space exploration and iteration, but also reveals limitations in verification and reproducibility, underscoring the importance of human-in-the-loop collaboration and future development of hardware-focused, instruction-tuned models.

Abstract

Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before synthesizing circuit elements. Automating this translation could reduce sources of human error from the engineering process. But, it is only recently that artificial intelligence (AI) has demonstrated capabilities for machine-based end-to-end design translations. Commercially-available instruction-tuned Large Language Models (LLMs) such as OpenAI's ChatGPT and Google's Bard claim to be able to produce code in a variety of programming languages; but studies examining them for hardware are still lacking. In this work, we thus explore the challenges faced and opportunities presented when leveraging these recent advances in LLMs for hardware design. Given that these `conversational' LLMs perform best when used interactively, we perform a case study where a hardware engineer co-architects a novel 8-bit accumulator-based microprocessor architecture with the LLM according to real-world hardware constraints. We then sent the processor to tapeout in a Skywater 130nm shuttle, meaning that this `Chip-Chat' resulted in what we believe to be the world's first wholly-AI-written HDL for tapeout.

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

TL;DR

The paper addresses the challenge of translating natural-language hardware specifications into HDL, proposing that conversational LLMs could serve as design assistants rather than full replacements for engineers. Through a case study with ChatGPT-4, the authors co-design an -bit accumulator-based microprocessor and achieve a tapeout with AI-written HDL, highlighting both the capabilities and the need for human intervention in specification and verification. Key contributions include the first hardware design study using conversational LLMs, an end-to-end workflow, and open data on logs and tooling, along with actionable recommendations for practitioners. The work demonstrates that conversational LLMs can accelerate design space exploration and iteration, but also reveals limitations in verification and reproducibility, underscoring the importance of human-in-the-loop collaboration and future development of hardware-focused, instruction-tuned models.

Abstract

Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before synthesizing circuit elements. Automating this translation could reduce sources of human error from the engineering process. But, it is only recently that artificial intelligence (AI) has demonstrated capabilities for machine-based end-to-end design translations. Commercially-available instruction-tuned Large Language Models (LLMs) such as OpenAI's ChatGPT and Google's Bard claim to be able to produce code in a variety of programming languages; but studies examining them for hardware are still lacking. In this work, we thus explore the challenges faced and opportunities presented when leveraging these recent advances in LLMs for hardware design. Given that these `conversational' LLMs perform best when used interactively, we perform a case study where a hardware engineer co-architects a novel 8-bit accumulator-based microprocessor architecture with the LLM according to real-world hardware constraints. We then sent the processor to tapeout in a Skywater 130nm shuttle, meaning that this `Chip-Chat' resulted in what we believe to be the world's first wholly-AI-written HDL for tapeout.
Paper Structure (19 sections, 8 figures, 3 tables)

This paper contains 19 sections, 8 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Trends in hardware design
  3. Automating Hardware Description Languages (HDLs)
  4. Contributions
  5. Background and Related Work
  6. Large Language Models (LLMs)
  7. Large Language Models for hardware design
  8. Instruction-tuned 'conversational' models
  9. LLM Assisted Design Space Exploration (Chip Chat)
  10. Overview
  11. Design Task: An 8-bit accumulator-based microprocessor
  12. Method: Conversation flow
  13. ISA Development
  14. Results: Processor implementation
  15. Observations
  16. ...and 4 more sections

Figures (8)

  • Figure 1: Can conversational LLMs be used to iteratively design hardware?
  • Figure 2: 8-bit accumulator-based processor: Starting design prompt
  • Figure 3: Portion of a conversation (Topic ID 15) asking ChatGPT to fix a bug in one of the Verilog modules that it had previously authored.
  • Figure 4: The most difficult prompt (10 restarts), which was provided in Topic 04 after ChatGPT-4 produced a list of datapath control signals and definitions.
  • Figure 5: Code produced by ChatGPT-4 for difficult prompt (11th attempt). It is still missing some I/O, corrected by later messages.
  • ...and 3 more figures