Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

TL;DR

This work introduces Big-PERCIVAL, a $RV64$-based RISC-V core extension that provides native $64$-bit posit arithmetic with an optional $1024$-bit quire for high-precision scientific computing. By evaluating across PolyBench, Conjugate Gradient, and GEMM on FPGA/ASIC targets, the authors demonstrate that $64$-bit posits can achieve up to $4$ orders of magnitude higher accuracy than $64$-bit doubles while maintaining similar memory bandwidth, albeit at a substantial hardware cost dominated by the quire and division/sqrt units. The study shows that quire-enabled posits improve accuracy and, in many kernels, convergence speed for iterative solvers, but can degrade timing in memory-bound kernels like GEMM due to accumulation ordering. Overall, the paper positions posit arithmetic as a promising but resource-intensive alternative to IEEE 754 for HPC, providing a concrete platform and empirical data to guide future hardware/software co-design.

Abstract

The accuracy requirements in many scientific computing workloads result in the use of double-precision floating-point arithmetic in the execution kernels. Nevertheless, emerging real-number representations, such as posit arithmetic, show promise in delivering even higher accuracy in such computations. In this work, we explore the native use of 64-bit posits in a series of numerical benchmarks and compare their timing performance, accuracy and hardware cost to IEEE 754 doubles. In addition, we also study the conjugate gradient method for numerically solving systems of linear equations in real-world applications. For this, we extend the PERCIVAL RISC-V core and the Xposit custom RISC-V extension with posit64 and quire operations. Results show that posit64 can obtain up to 4 orders of magnitude lower mean square error than doubles. This leads to a reduction in the number of iterations required for convergence in some iterative solvers. However, leveraging the quire accumulator register can limit the order of some operations such as matrix multiplications. Furthermore, detailed FPGA and ASIC synthesis results highlight the significant hardware cost of 64-bit posit arithmetic and quire. Despite this, the large accuracy improvements achieved with the same memory bandwidth suggest that posit arithmetic may provide a potential alternative representation for scientific computing.

Figures (13)

• Figure 1: Posit format with sign, regime, exponent, and fraction fields.
• Figure 2: Decoding example of a posit16.
• Figure 3: Block diagram of Big-PERCIVAL. Extended modules are highlighted in green. The with the new posit64 units is shown in orange.
• Figure 4: Internal structure of the PAU. The modifiable blocks with SystemVerilog parameters are shown in green.
• Figure 5: PolyBench benchmarks mean square error of the different arithmetics studied with respect to the results obtained with GNU MPFR.