PULSE: Accelerating Distributed Pointer-Traversals on Disaggregated Memory (Extended Version)

TL;DR

The paper tackles the bottleneck of pointer traversals in rack-scale disaggregated memory by introducing pulse, a near-memory, distributed traversal framework that uses an iterator-based programming model, a disaggregated accelerator with separate logic and memory pipelines, and in-network switch routing for cross-node traversals. By translating iterator code to a compact pulse ISA and offloading memory-centric work only when beneficial, pulse achieves high utilization and energy efficiency, achieving $t_c \leq \eta t_d$ with $\eta$ dynamically set by pipeline configuration. Real-system experiments show substantial gains: 9–34× lower latency, 28–171× higher throughput, and 4.5–5× lower energy per operation compared to RPC-based approaches, with potential further improvements if implemented in ASICs. The work demonstrates a scalable path to expressive, efficient distributed traversal across disaggregated memory, enabling broader adoption of memory-disaggregated architectures for pointer-heavy workloads.

Abstract

Caches at CPU nodes in disaggregated memory architectures amortize the high data access latency over the network. However, such caches are fundamentally unable to improve performance for workloads requiring pointer traversals across linked data structures. We argue for accelerating these pointer traversals closer to disaggregated memory in a manner that preserves expressiveness for supporting various linked structures, ensures energy efficiency and performance, and supports distributed execution. We design PULSE, a distributed pointer-traversal framework for rack-scale disaggregated memory to meet all the above requirements. Our evaluation of PULSE shows that it enables low-latency, high-throughput, and energy-efficient execution for a wide range of pointer traversal workloads on disaggregated memory that fare poorly with caching alone.

Figures (18)

• Figure 1: Need for accelerating pointer traversals.(top) The performance of pointer traversals in disaggregated architectures is bottlenecked by slow memory interconnect. (bottom) Just as caches offer limited but fast memory near CPUs, we argue that memory needs a counterpart for traversal-heavy workloads: a lightweight but fast accelerator for cache-unfriendly pointer traversals.
• Figure 1: Time cloud applications spend in pointer traversals based on prior studies
• Figure 2: Time cloud applications spend in pointer traversals. See §\ref{['ssec:need']} for details.
• Figure 2: Network and memory bandwidth utilization.pulse and RPC utilize over 90% of the available memory bandwidth, while the cache-based approach suffers from swap system overhead. In Webservice, the network bandwidth becomes the bottleneck due to large 8 KB data transfers.
• Figure 3: pulse Overview. Developers use pulse's iterator interface (§\ref{['sec:interface']}) to express pointer traversals, translated to pulse ISA by its dispatch engine (§\ref{['ssec:compute_node']}). During execution, pulse accelerator ensures energy efficiency (§\ref{['ssec:architecture']}) and in-network design enable distributed traversals (§\ref{['sec:distributed']}).