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Hardware implementation of digital memcomputing on small-size FPGAs

Dyk Chung Nguyen, Yuan-Hang Zhang, Massimiliano Di Ventra, Yuriy V. Pershin

TL;DR

This paper addresses solving combinatorial optimization via digital memcomputing machines (DMMs) by implementing a 3-SAT solver on a low-cost FPGA. It presents the DMM ODEs with continuous variables and memory per clause, then demonstrates a hardware realization using a hybrid forward-Euler integration scheme that partially parallelizes the computation. The authors report a 1–2 order of magnitude speed-up over a CPU-based Python implementation and provide scalability analyses suggesting that modern FPGAs could handle substantially larger problem sizes (tens to hundreds of thousands of variables) with continued hardware acceleration benefits. The work establishes hardware memcomputing as a viable approach for fast, scalable combinatorial optimization and highlights concrete roadmap steps for deployment on larger FPGA platforms and further architectural optimizations.

Abstract

Memcomputing is a novel computing paradigm beyond the von-Neumann one. Its digital version is designed for the efficient solution of combinatorial optimization problems, which emerge in various fields of science and technology. Previously, the performance of digital memcomputing machines (DMMs) was demonstrated using software simulations of their ordinary differential equations. Here, we present the first hardware realization of a DMM algorithm on a low-cost FPGA board. In this demonstration, we have implemented a Boolean satisfiability problem solver. To optimize the use of hardware resources, the algorithm was partially parallelized. The scalability of the present implementation is explored and our FPGA-based results are compared to those obtained using a python code running on a traditional (von-Neumann) computer, showing one to two orders of magnitude speed-up in time to solution. This initial small-scale implementation is projected to state-of-the-art FPGA boards anticipating further advantages of the hardware realization of DMMs over their software emulation.

Hardware implementation of digital memcomputing on small-size FPGAs

TL;DR

This paper addresses solving combinatorial optimization via digital memcomputing machines (DMMs) by implementing a 3-SAT solver on a low-cost FPGA. It presents the DMM ODEs with continuous variables and memory per clause, then demonstrates a hardware realization using a hybrid forward-Euler integration scheme that partially parallelizes the computation. The authors report a 1–2 order of magnitude speed-up over a CPU-based Python implementation and provide scalability analyses suggesting that modern FPGAs could handle substantially larger problem sizes (tens to hundreds of thousands of variables) with continued hardware acceleration benefits. The work establishes hardware memcomputing as a viable approach for fast, scalable combinatorial optimization and highlights concrete roadmap steps for deployment on larger FPGA platforms and further architectural optimizations.

Abstract

Memcomputing is a novel computing paradigm beyond the von-Neumann one. Its digital version is designed for the efficient solution of combinatorial optimization problems, which emerge in various fields of science and technology. Previously, the performance of digital memcomputing machines (DMMs) was demonstrated using software simulations of their ordinary differential equations. Here, we present the first hardware realization of a DMM algorithm on a low-cost FPGA board. In this demonstration, we have implemented a Boolean satisfiability problem solver. To optimize the use of hardware resources, the algorithm was partially parallelized. The scalability of the present implementation is explored and our FPGA-based results are compared to those obtained using a python code running on a traditional (von-Neumann) computer, showing one to two orders of magnitude speed-up in time to solution. This initial small-scale implementation is projected to state-of-the-art FPGA boards anticipating further advantages of the hardware realization of DMMs over their software emulation.
Paper Structure (10 sections, 3 equations, 4 figures)

This paper contains 10 sections, 3 equations, 4 figures.

Table of Contents

  1. Introduction
  2. memcomputing equations for 3-SAT
  3. Related work
  4. Methods
  5. Generation of SAT instances
  6. FPGA implementation
  7. Python code
  8. Results
  9. Discussion
  10. Conclusion

Figures (4)

  • Figure 1: Schematics of the parallerization of the memcomputing model. See the text for details.
  • Figure 2: Time to reach the solution, $T_\textnormal{FPGA}$, as the function of the number of variables for (a) $M/N=4.3$ and (b) $M/N=7$ using FPGA board. Median times were used to obtain the fits (see the text).
  • Figure 3: The ratio of the python code calculation time to FPGA calculation time, $T_\textnormal{python}/T_\textnormal{FPGA}$. Each point was obtained for the same problem instance and initial conditions.
  • Figure 4: Utilization of LUTs depending on the problem size. The dashed horizontal lines denote the maximum number of LUTs in our small-size FPGA board and VCU118 evaluation board. Inset: LUTs requirement for a larger board obtained using VIVADO synthesis. The fitting curves are $f_1(N)=5226+582\cdot N$ and $f_2(N)=134147+132\cdot N$.