LearnedFTL: A Learning-Based Page-Level FTL for Reducing Double Reads in Flash-Based SSDs

TL;DR

LearnedFTL addresses the double-read penalty in flash-based SSDs by integrating a lightweight learned-index based address translation with an existing demand-based FTL. The design introduces an in-place-update PLR model with a bitmap filter, a virtual PPN representation to align training data with SSD parallelism, and a group-based allocation plus GC/rewrite strategy to curb training overhead. Empirical results on a FEMU prototype show up to 55.5% reduction in address-translation-induced double reads and substantial tail-latency improvements (up to 12.2×) over state-of-the-art TPFTL and LeaFTL, while maintaining competitive read/write energy profiles. The work demonstrates that carefully engineered learned-index components can augment FTL performance without large-scale architectural changes, enabling better random and mixed workload performance in modern SSDs.

Abstract

We present LearnedFTL, a new on-demand page-level flash translation layer (FTL) design, which employs learned indexes to improve the address translation efficiency of flash-based SSDs. The first of its kind, it reduces the number of double reads induced by address translation in random read accesses. LearnedFTL proposes three key techniques: an in-place-update linear model to build learned indexes efficiently, a virtual PPN representation to obtain contiguous PPNs for sorted LPNs, and a group-based allocation and model training via GC/rewrite strategy to reduce the training overhead. By tightly integrating the aforementioned key techniques, LearnedFTL considerably speeds up address translation while reducing the number of flash read accesses caused by the address translation. Our extensive experiments on a FEMU-based prototype show that LearnedFTL can reduce up to 55.5\% address translation-induced double reads. As a result, LearnedFTL reduces the P99 tail latency by 2.9$\times$ $\sim$ 12.2$\times$ with an average of 5.5$\times$ and 8.2$\times$ compared to the state-of-the-art TPFTL and LeaFTL schemes, respectively.

Figures (22)

• Figure 1: Representative mapping schemes in flash-based SSDs.
• Figure 2: The performance of a FEMU-emulated SSD under sequential reads and random reads.
• Figure 3: The hit ratio of TPFTL under different CMT space.
• Figure 4: The workflow of the learned index.
• Figure 5: The workflow of triple reads in LeaFTL sun2023leaftl.