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Balanced Low-Complexity and Flexible Error-Correction List Flip Decoding for Polar Codes

Yansong Lv, Jingxin Dai, Yuhuan Wang, Hang Yin, Zhanxin Yang

TL;DR

This work addresses the need for polar decoders that combine flexible high-order error-correction with low average complexity. It introduces the parity-check-aided D-SCLF (PC-DSCLF) decoder, which couples a simplified flip metric with a hybrid parity-check scheme to enable early termination and effective error detection without increasing computational burden. Simulation results show substantial complexity reductions (up to 64.1% on average) while maintaining FER performance comparable to or better than existing FHECC decoders, including a 51.1% reduction in the average path count $D$ for PC(512,256+24) relative to D-SCLF with distributed CRC. The proposed approach is practical for IoT and other high-reliability, low-power scenarios where polar codes are advantageous at short block lengths.

Abstract

Benefiting from performance advantages under short code lengths, polar codes are well-suited for certain scenarios, such as the future Internet of Things (IoT) applications that require high reliability and low power. Existing list flip decoders can efficiently further enhance the error-correction performance of polar codes with finite code lengths, particularly the dynamic successive cancellation list flip (D-SCLF) decoder with flexible high-order error-correction capability (FHECC). However, to the best of our knowledge, current list flip decoders cannot effectively balance complexity and error-correction efficiency. To address this, we propose a parity-check-aided D-SCLF (PC-DSCLF) decoder. This decoder, based on FHECC and the characteristics of the list flip decoding process, introduces a simplified flip metric and a hybrid check scheme, along with a decoding method that supports the check scheme, enabling it to retain FHECC while achieving low complexity. Simulation results show that the proposed PC-DSCLF decoder achieves up to a 51.1\% average complexity reduction compared to the D-SCLF algorithm with distributed CRC for $PC(512, 256+24)$

Balanced Low-Complexity and Flexible Error-Correction List Flip Decoding for Polar Codes

TL;DR

This work addresses the need for polar decoders that combine flexible high-order error-correction with low average complexity. It introduces the parity-check-aided D-SCLF (PC-DSCLF) decoder, which couples a simplified flip metric with a hybrid parity-check scheme to enable early termination and effective error detection without increasing computational burden. Simulation results show substantial complexity reductions (up to 64.1% on average) while maintaining FER performance comparable to or better than existing FHECC decoders, including a 51.1% reduction in the average path count for PC(512,256+24) relative to D-SCLF with distributed CRC. The proposed approach is practical for IoT and other high-reliability, low-power scenarios where polar codes are advantageous at short block lengths.

Abstract

Benefiting from performance advantages under short code lengths, polar codes are well-suited for certain scenarios, such as the future Internet of Things (IoT) applications that require high reliability and low power. Existing list flip decoders can efficiently further enhance the error-correction performance of polar codes with finite code lengths, particularly the dynamic successive cancellation list flip (D-SCLF) decoder with flexible high-order error-correction capability (FHECC). However, to the best of our knowledge, current list flip decoders cannot effectively balance complexity and error-correction efficiency. To address this, we propose a parity-check-aided D-SCLF (PC-DSCLF) decoder. This decoder, based on FHECC and the characteristics of the list flip decoding process, introduces a simplified flip metric and a hybrid check scheme, along with a decoding method that supports the check scheme, enabling it to retain FHECC while achieving low complexity. Simulation results show that the proposed PC-DSCLF decoder achieves up to a 51.1\% average complexity reduction compared to the D-SCLF algorithm with distributed CRC for
Paper Structure (11 sections, 1 theorem, 22 equations, 10 figures, 4 algorithms)

This paper contains 11 sections, 1 theorem, 22 equations, 10 figures, 4 algorithms.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Polar Encoding Method
  4. CA-SCL Decoder
  5. List Flip Decoder
  6. PC-DSCLF Decoder
  7. Simplified Flip Metric for the D-SCLF Decoder
  8. Hybrid Check Scheme for the D-SCLF Decoder
  9. Details of the PC-DSCLF decoder
  10. Simulation Results and Discussions
  11. Conclusions

Key Result

Theorem 1

The PC-DSCLF decoder cannot execute the inserted flip set ${\mathcal{S}_t \cup {j} }$ before the $t^{th}$ additional attempt.

Figures (10)

  • Figure 1: FER performance comparison of D-SCLF2 with different conditions.
  • Figure 2: An example of our allocation schemes with 3 PC bits for a hypothetical non-frozen bits sequence.
  • Figure 3: FER performance comparison between D-SCLF2 (24 undistributed CRC bits) and PC-DSCLF2 (8 PC bits and 16 undistributed CRC bits), both with the same $f_{\beta=0.4}$ and $L=4$.
  • Figure 4: $D$ comparison between D-SCLF2 (24 undistributed CRC bits) and PC-DSCLF2 (8 PC bits and 16 undistributed CRC bits), both with the same $f_{\beta=0.4}$ and $L=4$.
  • Figure 5: FER performance comparison of the PC-DSCLF2 (8 PC bits and 16 undistributed CRC bits) algorithms with different flip metrics.
  • ...and 5 more figures

Theorems & Definitions (1)

  • Theorem 1