Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

TL;DR

This work tackles the challenge of reliable onboard space computing without the prohibitive cost of traditional radiation-hardened designs. It introduces Hybrid Modular Redundancy (HMR), a runtime-configurable, open-source RISC-V cluster that can operate in independent, dual-core lockstep, or triple-core lockstep, with both software- and hardware-assisted recovery options and a fast split-lock mechanism. Key contributions include a full hardware unit enabling on-demand redundancy, fast rapid-recovery hardware (24 cycles), cycle-accurate TCLS-style software resynchronization, and runtime partitioning between mission-critical and performance sections, all demonstrated on a 12-core CV32E40P cluster at 430 MHz with modest area overhead. The findings show substantial compute gains in redundant modes, low recovery latency, and real-time fault management capabilities, making the approach viable for space missions requiring reliable yet efficient onboard processing and enabling an open-source reference design for future research and deployment.

Abstract

Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying solely on radiation-hardened technologies is extremely expensive, and developing inflexible architectural and microarchitectural modifications to introduce modular redundancy within a system leads to significant area increase and performance degradation. To mitigate the overheads of traditional radiation hardening and modular redundancy approaches, we present a novel Hybrid Modular Redundancy (HMR) approach, a redundancy scheme that features a cluster of RISC-V processors with a flexible on-demand dual-core and triple-core lockstep grouping of computing cores with runtime split-lock capabilities. Further, we propose two recovery approaches, software-based and hardware-based, trading off performance and area overhead. Running at 430 MHz, our fault-tolerant cluster achieves up to 1160 MOPS on a matrix multiplication benchmark when configured in non-redundant mode and 617 and 414 MOPS in dual and triple mode, respectively. A software-based recovery in triple mode requires 363 clock cycles and occupies 0.612 mm2, representing a 1.3% area overhead over a non-redundant 12-core RISC-V cluster. As a high-performance alternative, a new hardware-based method provides rapid fault recovery in just 24 clock cycles and occupies 0.660 mm2, namely ~9.4% area overhead over the baseline non-redundant RISC-V cluster. The cluster is also enhanced with split-lock capabilities to enter one of the redundant modes with minimum performance loss, allowing execution of a mission-critical or a performance section, with <400 clock cycles overhead for entry and exit. The proposed system is the first to integrate these functionalities on an open-source RISC-V-based compute device, enabling finely tunable reliability vs. performance trade-offs.

Figures (10)

• Figure 1: Integration of the unit within the cluster.
• Figure 2: dmode grouped cores.
• Figure 3: tmode grouped cores.
• Figure 4: Split-Lock muxing example for a 6-core group configuration.
• Figure 5: of the controller.