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An Implementation of the Optimal Scheme for Energy Efficient Bus Encoding

Lorenzo Valentini, Marco Chiani

TL;DR

The work addresses energy efficiency in binary bus interconnects by implementing the optimal differential bus-encoding scheme that minimizes the average number of transitions between successive codewords. It derives the optimal codebook and offers several practical hardware realizations, including Data Bus Inversion (DBI) for minimal redundancy, a maximum-redundancy PPM0 approach, a syndrome-decoder based coset-code implementation, and a combinatorial-number-system–based MPPM scheme. The authors discuss encoder/decoder complexity and demonstrate energy-saving potential relative to uncoded buses, highlighting trade-offs between added lines and transition reductions across different parameter regimes. These results provide hardware-friendly strategies for NoC, memory interfaces, and AI accelerators, enabling scalable, energy-efficient bus encoding in modern architectures.

Abstract

In computer system buses, most of the energy is spent to change the voltage of each line from high to low or vice versa. Bus encoding schemes aim to improve energy efficiency by limiting the number of transitions between successive uses of the bus. We propose an implementation of the optimal code with reduced number of clock cycles.

An Implementation of the Optimal Scheme for Energy Efficient Bus Encoding

TL;DR

The work addresses energy efficiency in binary bus interconnects by implementing the optimal differential bus-encoding scheme that minimizes the average number of transitions between successive codewords. It derives the optimal codebook and offers several practical hardware realizations, including Data Bus Inversion (DBI) for minimal redundancy, a maximum-redundancy PPM0 approach, a syndrome-decoder based coset-code implementation, and a combinatorial-number-system–based MPPM scheme. The authors discuss encoder/decoder complexity and demonstrate energy-saving potential relative to uncoded buses, highlighting trade-offs between added lines and transition reductions across different parameter regimes. These results provide hardware-friendly strategies for NoC, memory interfaces, and AI accelerators, enabling scalable, energy-efficient bus encoding in modern architectures.

Abstract

In computer system buses, most of the energy is spent to change the voltage of each line from high to low or vice versa. Bus encoding schemes aim to improve energy efficiency by limiting the number of transitions between successive uses of the bus. We propose an implementation of the optimal code with reduced number of clock cycles.
Paper Structure (9 sections, 13 equations, 4 figures)

This paper contains 9 sections, 13 equations, 4 figures.

Table of Contents

  1. Introduction
  2. General Framework
  3. Problem Formulation
  4. Minimum Achievable Average Distance
  5. Optimal Code Implementations
  6. Minimum Redundancy Case: Data Bus Inversion
  7. Maximum Redundancy Case: PPM$_0$
  8. Implementation based on syndrome decoders (coset codes)
  9. Implementation Based on Combinatorial Number System

Figures (4)

  • Figure 1: General Framework.
  • Figure 2: Syndrome-based low-weight codes for bus encoding.
  • Figure 3: Implementation of a MPPM modulator using pre-allocated binomial coefficients. The scheme is able to compute $\text{MPPM}\left(x; \,m\right)$ in $m$ clocks.
  • Figure 4: Energy saving $1-D_\mathrm{opt}(k,b)/D_\mathrm{unc}(k)$ for the Optimal Bus Encoding Scheme, information size $k=11$.