Monad: Towards Cost-effective Specialization for Chiplet-based Spatial Accelerators

TL;DR

Monad addresses cost-aware co-design for chiplet-based spatial accelerators by jointly exploring architectural and packaging options under non-uniform dataflow and communications. It introduces a modeling framework and an ML-driven optimization engine that co-optimizes resource assignment, dataflow, network, and packaging to balance power, performance, price, and area. The approach achieves substantial $EDP$ reductions compared with Simba and NN-Baton and reveals a rich design space where cost is a first-class objective. This work enables practical, scalable design of specialized chiplet systems for tensor workloads with realistic packaging constraints.

Abstract

Advanced packaging offers a new design paradigm in the post-Moore era, where many small chiplets can be assembled into a large system. Based on heterogeneous integration, a chiplet-based accelerator can be highly specialized for a specific workload, demonstrating extreme efficiency and cost reduction. To fully leverage this potential, it is critical to explore both the architectural design space for individual chiplets and different integration options to assemble these chiplets, which have yet to be fully exploited by existing proposals. This paper proposes Monad, a cost-aware specialization approach for chiplet-based spatial accelerators that explores the tradeoffs between PPA and fabrication costs. To evaluate a specialized system, we introduce a modeling framework considering the non-uniformity in dataflow, pipelining, and communications when executing multiple tensor workloads on different chiplets. We propose to combine the architecture and integration design space by uniformly encoding the design aspects for both spaces and exploring them with a systematic ML-based approach. The experiments demonstrate that Monad can achieve an average of 16% and 30% EDP reduction compared with the state-of-the-art chiplet-based accelerators, Simba and NN-Baton, respectively.

Figures (10)

• Figure 1: A chiplet-based spatial accelerator with distributed compute and memory elements
• Figure 2: Typical advanced packaging technologies
• Figure 3: Cost comparison for TPU and Gemmini (Gem)
• Figure 4: The mapping formulation. The red arrows represent data transfers, and the dashed blue lines represent pipelining stages.
• Figure 5: Execution diagrams. $e_{0,2}$ is data transfer from chiplet 0 to 2 and $e_{1,2}$ is data transfer from chiplet 1 to 2. With a linear topology and a fair allocation policy, only half of the link bandwidth can be occupied by $e_{0,2}$.