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Design for Trust utilizing Rareness Reduction

Aruna Jayasena, Prabhat Mishra

TL;DR

Hardware Trojans can be concealed in outsourced SoC designs by exploiting rare-trigger events. The paper proposes rareness reduction as a design-for-trust strategy, combining a theoretical framework (definitions, ITM-based analysis, and metrics) with two practical techniques: design diversity and area optimization. It demonstrates a formal link between design area and security, and validates that reducing rareness accelerates Trojan detection using statistical test generation (MERO) and clique-based activation (TARMAC) on real benchmarks. The findings show that area-optimized, diverse designs yield higher rareness metrics, faster detection, and better Trojan coverage, enabling more trustworthy hardware in supply chains.

Abstract

Increasing design complexity and reduced time-to-market have motivated manufacturers to outsource some parts of the System-on-Chip (SoC) design flow to third-party vendors. This provides an opportunity for attackers to introduce hardware Trojans by constructing stealthy triggers consisting of rare events (e.g., rare signals, states, and transitions). There are promising test generation-based hardware Trojan detection techniques that rely on the activation of rare events. In this paper, we investigate rareness reduction as a design-for-trust solution to make it harder for an adversary to hide Trojans (easier for Trojan detection). Specifically, we analyze different avenues to reduce the potential rare trigger cases, including design diversity and area optimization. While there is a good understanding of the relationship between area, power, energy, and performance, this research provides a better insight into the dependency between area and security. Our experimental evaluation demonstrates that area reduction leads to a reduction in rareness. It also reveals that reducing rareness leads to faster Trojan detection as well as improved coverage by Trojan detection methods.

Design for Trust utilizing Rareness Reduction

TL;DR

Hardware Trojans can be concealed in outsourced SoC designs by exploiting rare-trigger events. The paper proposes rareness reduction as a design-for-trust strategy, combining a theoretical framework (definitions, ITM-based analysis, and metrics) with two practical techniques: design diversity and area optimization. It demonstrates a formal link between design area and security, and validates that reducing rareness accelerates Trojan detection using statistical test generation (MERO) and clique-based activation (TARMAC) on real benchmarks. The findings show that area-optimized, diverse designs yield higher rareness metrics, faster detection, and better Trojan coverage, enabling more trustworthy hardware in supply chains.

Abstract

Increasing design complexity and reduced time-to-market have motivated manufacturers to outsource some parts of the System-on-Chip (SoC) design flow to third-party vendors. This provides an opportunity for attackers to introduce hardware Trojans by constructing stealthy triggers consisting of rare events (e.g., rare signals, states, and transitions). There are promising test generation-based hardware Trojan detection techniques that rely on the activation of rare events. In this paper, we investigate rareness reduction as a design-for-trust solution to make it harder for an adversary to hide Trojans (easier for Trojan detection). Specifically, we analyze different avenues to reduce the potential rare trigger cases, including design diversity and area optimization. While there is a good understanding of the relationship between area, power, energy, and performance, this research provides a better insight into the dependency between area and security. Our experimental evaluation demonstrates that area reduction leads to a reduction in rareness. It also reveals that reducing rareness leads to faster Trojan detection as well as improved coverage by Trojan detection methods.
Paper Structure (24 sections, 6 equations, 10 figures, 2 tables)

This paper contains 24 sections, 6 equations, 10 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Threat Model
  3. Limitations of Existing Methods
  4. Research Contributions
  5. Rareness Reduction
  6. Definitions
  7. Metrics
  8. Theoretical Analysis
  9. Calculating the Logic Probability Vector of a Signal
  10. Effect of Logic Gate Types in the Path on Rareness
  11. Effect of Logic Depth on Rareness
  12. Effect of Area Optimization on Rareness
  13. Rareness Reduction Techniques
  14. Design Diversity
  15. Area Optimization
  16. ...and 9 more sections

Figures (10)

  • Figure 1: Hardware Trojan triggered by two rare signals (p,q)
  • Figure 2: Overview of proposed rareness reduction based design-for-trust improvement.
  • Figure 3: Calculating the rareness probability for a signal ($Z$) when fan-in signals ($A,B$) propagate through an AND gate.
  • Figure 4: An example to illustrate the effect of gate type in rareness propagation through logic depth.
  • Figure 5: An example scenario of rareness reduction of logic circuits through area optimization
  • ...and 5 more figures