A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/$^\circ$C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI

Abstract

In many applications, the ability of current references to cope with process, voltage, and temperature (PVT) variations is critical to maintaining system-level performance. However, temperature-independent current references operating in the nA range are rarely area-efficient due to the use of large resistors which occupy a significant silicon area at this current level. In this article, we introduce a nA-range constant-with-temperature (CWT) current reference relying on a self-cascode MOSFET (SCM), biased by a proportional-to-absolute-temperature (PTAT) voltage with a CWT offset. On the one hand, the proposed reference has been simulated post-layout in 65-nm bulk. This design consumes 5.4 nW at 0.7 V and achieves a 1.1-nA current with a line sensitivity (LS) of 0.69 %/V and a temperature coefficient (TC) of 213 ppm/$^\circ$C. On the other hand, the proposed reference has been simulated and fabricated in 22-nm fully depleted silicon-on-insulator (FDSOI). This second design requires additional features to mitigate the impact of parasitic diode leakage at high temperature. In measurement, it consumes 5.8 nW at 0.9 V and achieves a 0.9-nA current with a 0.39-%/V LS and a 565-ppm/$^\circ$C TC. As a result of using an SCM, the proposed references occupy a silicon area of 0.0021 mm$^2$ in 65 nm (respectively, 0.0132 mm$^2$ in 22 nm) at least 25$\times$ (respectively, 4$\times$) smaller than state-of-the-art CWT references operating in the same current range.

Figures (25)

• Figure 1: (a) Trade-off between silicon area and reference current, based on prior art, highlighting the absence of area-efficient solutions for the generation of a nA-range CWT current. (b) Conventional CWT current references are based on a reference voltage applied to a gate-leakage transistor or a resistor, which are respectively well suited to the generation of a pA- or $\mu$A-range current.
• Figure 2: Basic schematic of the proposed current reference, which consists of an SCM formed by $M_{1-2}$ (in blue) and further simplified in (b), and a $\beta$-multiplier composed of $M_{6-7}$ (in orange) summarized in (c).
• Figure 3: Operation principle of PTAT references proposed in prior art CamachoGaleano_2005CamachoGaleano_2008 (in orange) and of the proposed CWT reference (in blue). Analytical expression of (a) the voltage $V_X$ applied to the SCM, (b) the inversion level of $M_2$, denoted as $i_{f2}$, and (c) the reference current $I_{REF}$, as a function of temperature and for $\Delta V_T$ = 20 mV. Generic technological parameters $n$ = 1.2 and $m$ = 1.25 are selected. (b) and (c) are normalized by their value at 25$^\circ$C. For the proposed CWT reference, the parameters leading to a minimum $I_{REF}$ TC are $K_{PTAT} = 6$ and $\alpha = 2.9$.
• Figure 4: Analytical expression for (a) the TC of $I_{REF}$ and (b) the sensitivity $S_{I_{REF}}$, as a function of $K_{PTAT}$ and $\alpha$, and for the same technological parameters as Fig. \ref{['fig:3_operation_principle']}. (c) Location of the $I_{REF}$ TC valley in the $(K_{PTAT};\:\alpha)$ space, for $\Delta V_T$ ranging from 10 to 30 mV. (d) $I_{REF}$ TC and $S_{I_{REF}}$ as a function of $\Delta V_T$, for $\alpha = 4$ and the optimal value of $K_{PTAT}$.
• Figure 5: All figures correspond to 1-$\mu$m-wide standard-well pMOS devices simulated at 25$^\circ$C, and the threshold voltage is extracted from $g_m/I_D$ vs. $V_{SG}$ curves as described in Jespers_2017. $|V_{T0}|$ variations with the transistor length for (a) LVT, RVT and HVT core pMOS in 65-nm bulk and (b) LVT and ULL I/O pMOS in 22-nm FDSOI. For 1-$\mu$m-long devices, (c) $|V_T|$ and (d) $d|V_T|/dV_{SB}$ with $V_{SB}$ for 65- and 22-nm devices. $V_{SB}$ is limited by 0.7 V in 65 nm, to avoid the forward biasing of the parasitic diode between the transistor's source and body, and by the 1.8-V supply voltage in 22 nm.