4-clique Network Minor Embedding for Quantum Annealers

TL;DR

The paper addresses embedding complex optimization problems onto sparsely connected quantum annealers by introducing a 4-clique network minor embedding that operates on Pegasus hardware, which is rich in 4-cliques. It develops a contraction-based construction to form chains of 4-cliques representing logical variables and analyzes implementation using hardware contraction and standard embedding tools like minorminer, with chain strengths and energy scaling discussed. Experiments on D-Wave Advantage Pegasus devices compare 4-clique embeddings to conventional linear-path embeddings across varying problem sizes, showing that 4-clique chains can reduce chain breaks at low chain strengths and preserve a larger portion of the hardware's energy range, particularly for larger problems, though at increased qubit overhead. The findings suggest potential utility for future, larger quantum annealers where long, high-integrity chains are unavoidable, while also highlighting limitations for current devices and outlining future directions, including non-uniform weights and structured embeddings to further balance chain integrity and coefficient precision.

Abstract

Quantum annealing is a quantum algorithm for computing solutions to combinatorial optimization problems. This study proposes a method for minor embedding optimization problems onto sparse quantum annealing hardware graphs called 4-clique network minor embedding. This method is in contrast to the standard minor embedding technique of using a path of linearly connected qubits in order to represent a logical variable state. The 4-clique minor embedding is possible on Pegasus graph connectivity, which is the native hardware graph for some of the current D-Wave quantum annealers. The Pegasus hardware graph contains many cliques of size 4, making it possible to form a graph composed entirely of paths of connected 4-cliques on which a problem can be minor embedded. The 4-clique chains come at the cost of additional qubit usage on the hardware graph, but they allow for stronger coupling within each chain thereby increasing chain integrity, reducing chain breaks, and allow for greater usage of the available energy scale for programming logical problem coefficients on current quantum annealers. The 4-clique minor embedding technique is compared against the standard linear path minor embedding with experiments on two D-Wave quantum annealing processors with Pegasus hardware graphs. We show proof of concept experiments where the 4-clique minor embeddings can use weak chain strengths while successfully carrying out the computation of minimizing random all-to-all spin glass problem instances.

Figures (11)

• Figure 1: A path of 4-cliques.
• Figure 2: Contracted 4-clique graph of Advantage_system4.1 with kamada kawai layout (top left), spring layout (top middle), and spectral layout (top right). Contracted 4-clique graph of Advantage_system6.1 with kamada kawai layout (bottom left), spring layout (bottom middle), and spectral layout (bottom right). The contracted 4-clique graph of Advantage_system4.1 has $2471$ nodes and $6270$ edges. The contracted 4-clique graph of Advantage_system6.1 has $2463$ nodes and $6245$ edges. As defined by Algorithm \ref{['algorithm:contract_hardware_graph']}, an edge in a contracted 4-clique graph represents $4$ edges in the underlying hardware graph, and a node represents $2$ physical qubits in the hardware graph. These contracted clique graphs are quite sparse; the maximum clique of both of these graphs are $2$. When the clique contraction is performed on the hardware graphs, there are many small unconnected components that are generated. These figures are showing only the largest connected component since it is the one which can be used for large minor embeddings.
• Figure 3: Minor-embedding of a $K_5$ clique onto the target graph connectivity of Pegasus, using a 4-clique minor embedding (left) and an equivalent linear path minor embedding (right). Nodes in the graph are physical qubits, and edges are physical couplers. Grey edges represent the physical couplers onto which the problem specific coefficients would be encoded. Colored edges and nodes denote the minor embeddings; each chain (comprised of qubits and couplers) is uniquely colored. Notice that the 4-clique minor embedding by default uses chains with length 2 as the smallest possible chains to encode a logical variable; these together form a single node pair $n_x$, $n_y$ that are two of the variables in a 4-clique in the hardware. The linear path embedding by contrast does use chains of length $1$ (meaning there is no chain). Qubits and couplers not used by the minor embedding are not shown. Because Pegasus natively has cliques of size 4, it makes no sense to actually use a minor-embedding of size 4. Therefore, this specific minor embedding diagram is purely for the purposes of describing the 4-clique minor embedding algorithm.
• Figure 4: Minor-embedding of a $K_8$ clique using a 4-clique minor embedding (left) and an equivalent linear path minor embedding (right) on a Pegasus graph. Grey edges represent the physical couplers onto which the problem specific coefficients would be encoded. Colored edges and nodes denote the minor embeddings; each chain (comprised of qubits and couplers) is uniquely colored. As in Figure \ref{['fig:minor_embedding_N4']}, the parts of the Pegasus graph which are not used by the minor embeddings are not shown.
• Figure 5: $K_{32}$ 4-clique minor embedding on the $P_{16}$ Pegasus hardware graphs of Advantage_system4.1 (left) and Advantage_system6.1 (right). Each of the $32$ chains are uniquely colored. These are the largest all-to-all 4-clique minor embeddings that could be computed using minorminer in a reasonable amount of time.