Restricting to the chip architecture maintains the quantum neural network accuracy

TL;DR

This work investigates how quantum chip connectivity affects variational quantum algorithms used in quantum neural networks. Through a theoretical framework centered on unitary $t$-designs and a series of simulations, the authors show that as the parameterization depth increases (approaching a $t$-design), the cost landscape concentrates around an architecture-averaged value $\mathbb{E}_{U}[C]$, making chip-constrained parametrizations viable and potentially reducing SWAP overhead. The simulations demonstrate that restricting gates to chip-neighboring qubits yields similar convergence trends to unrestricted cases for larger systems, and the observed concentration matches the theoretical bounds involving $d=2^{N}$ and $H$-dependent traces. The findings support designing VQAs that respect chip connectivity, offering practical pathways to lower-depth, more noise-resilient quantum learning on current hardware.

Abstract

In the era of noisy intermediate-scale quantum devices, variational quantum algorithms (VQAs) stand as a prominent strategy for constructing quantum machine learning models. These models comprise both a quantum and a classical component. The quantum facet is characterized by a parametrization $U$, typically derived from the composition of various quantum gates. On the other hand, the classical component involves an optimizer that adjusts the parameters of $U$ to minimize a cost function $C$. Despite the extensive applications of VQAs, several critical questions persist, such as determining the optimal gate sequence, devising efficient parameter optimization strategies, selecting appropriate cost functions, and understanding the influence of quantum chip architectures on the final results. This article aims to address the last question, emphasizing that, in general, the cost function tends to converge towards an average value as the utilized parameterization approaches a $2$-design. Consequently, when the parameterization closely aligns with a $2$-design, the quantum neural network model's outcome becomes less dependent on the specific parametrization. This insight leads to the possibility of leveraging the inherent architecture of quantum chips to define the parametrization for VQAs. By doing so, the need for additional swap gates is mitigated, consequently reducing the depth of VQAs and minimizing associated errors.

Figures (9)

• Figure 1: A) Illustration of the operation of variational quantum algorithms. These models work in a hybrid way, that is, using a quantum computer and a classical computer. In the quantum computer the quantum circuit will be run and in the classical computer the classical optimizer will be run. B) Illustration of a quantum circuit with three qubits.
• Figure 2: Illustration of IBM's Guadalupe chip connectivity architecture.
• Figure 3: Illustration of the $U_{l}W_{l}$ parametrization for the case where it is not fixed by the chip architecture.
• Figure 4: Example dataset used to train and test models of quantum neural networks. The red and blue dots are the training data. The yellow and green dots are test data.
• Figure 5: Illustration of the way data was encoded in a quantum state. In this example only three qubits are shown. However, the same encoding was used in all the experiments, independent of the number of qubits involved. In this example we show how input data with two elements $x_{0}$ and $x_{1}$ will be encoded in the quantum circuit.

Theorems & Definitions (5)

• Definition 1
• Theorem 1
• proof
• Corollary 1
• proof