Interaction graph-based characterization of quantum benchmarks for improving quantum circuit mapping techniques

TL;DR

The paper tackles the problem of quantum circuit mapping under hardware constraints by extending circuit profiling to include qubit interaction graphs. It introduces graph-theoretic metrics to characterize circuit structure, enabling clustering of benchmarks into families with similar mapping behavior and enabling cross-device performance comparisons. Experimental results across Surface-97, IBM Rochester, and Rigetti Aspen-16 show that interaction-graph properties correlate with mapping overhead and fidelity decrease, with the strength of these correlations depending on device topology. The work also delivers a comprehensive, open benchmark suite (QBench) to support future compiler and hardware research, and outlines directions for algorithm-aware mapping and circuit hardware co-design. Overall, incorporating interaction-graph structure into profiling enhances understanding of mapping performance and informs the selection of mappers and hardware configurations for targeted quantum workloads.

Abstract

To execute quantum circuits on a quantum processor, they must be modified to meet the physical constraints of the quantum device. This process, called quantum circuit mapping, results in a gate/circuit depth overhead that depends on both the circuit properties and the hardware constraints, being the limited qubit connectivity a crucial restriction. In this paper, we propose to extend the characterization of quantum circuits by including qubit interaction graph properties using graph theory-based metrics in addition to previously used circuit-describing parameters. This approach allows for in-depth analysis and clustering of quantum circuits and a comparison of performance when run on different quantum processors, aiding in developing better mapping techniques. Our study reveals a correlation between interaction graph-based parameters and mapping performance metrics for various existing configurations of quantum devices. We also provide a comprehensive collection of quantum circuits and algorithms for benchmarking future compilation techniques and quantum devices.

Figures (19)

• Figure 1: Running a quantum circuit on a 7-qubit quantum processor. (a) Interaction graph $G_i(V_i, E_i)$ of the circuit shown below; Nodes $V_i$ represent virtual qubits, and edges $E_i$ show interactions between qubits (i.e., 2-qubit gates). (b,c) The chip's coupling graph $G_c(V_c, E_c)$; Nodes $V_c$ represent physical qubits, edges $E_c$ show connections on the chip (i.e., possible two-qubit interactions). (d) Circuit qubits ($qi \in V_i$) are mapped onto physical qubits ($Qi \in V_c$). (e) An extra SWAP gate is required to be able to perform all CNOT gates.
• Figure 2: (a) Circuit fidelity vs. the number of gates. (b) Gate overhead (%) and decrease in fidelity. Synthetically generated circuits marked with orange circles and real ones (i.e., quantum algorithms and routines) with blue squares. Here, only circuits with up to 500 gates were used.
• Figure 3: Interaction graphs of circuits with same size-related parameters: no. of qubits = 6, no. of gates = 456, two-qubit gate percentage = 0.135.
• Figure 4: Heatmap of a Pearson correlation matrix for quantum circuit and interaction graph metrics selected for mapping.
• Figure 5: Clustering of quantum algorithms based on size-related parameters.