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Non-Linear Analog Processing in MIMO Systems with Coarse Quantization

Marian Temprana Alonso, Xuyang Liu, Hamidreza Aghasi, Farhad Shirani

TL;DR

The paper tackles the power bottleneck of ADCs in mmWave MIMO receivers by introducing nonlinear analog processing—envelope detectors and polynomial operators—before sampling and low-resolution quantization. It develops a unified framework linking analog front-end design to achievable rates under a total ADC power budget, derives capacity bounds and inner bounds for SISO and hybrid MIMO setups, and demonstrates how nonlinear processing can mitigate the curse of low dimensions that hampers rate scaling with the number of ADCs. The key contributions include theoretical capacity results for envelope-detector and polynomial-based front-ends, a practical hybrid-beamforming quantizer design achieving notable high-SNR gains, and circuit-level simulations and measurements across 22 nm FDSOI and 65 nm bulk CMOS showing improved rate-power tradeoffs. The findings suggest that carefully engineered nonlinear analog processing can substantially reduce rate loss due to coarse quantization while maintaining favorable power profiles, with clear guidance for mmWave receiver architectures and circuit implementations.

Abstract

Analog to digital converters (ADCs) are a major contributor to the power consumption of multiple-input multiple-output (MIMO) receivers in large bandwidth millimeter-wave systems. Prior works have considered two mitigating solutions to reduce the ADC power consumption: i) decreasing the number of ADCs via analog and hybrid beamforming, and ii) decreasing the ADC resolution, i.e., utilizing one-bit and few-bit ADCs. These mitigating solutions lead to performance loss in terms of achievable rates due to increased quantization error. In this work, the use of nonlinear analog operators such as envelope detectors and polynomial operators, prior to sampling and quantization is considered, as a way to reduce the aforementioned rate-loss. The receiver architecture consists of linear combiners, nonlinear analog operators, and few-bit ADCs. The fundamental performance limits of the resulting communication system, in terms of achievable rates, are investigated under various assumptions on the set of implementable analog operators. Extensive numerical evaluations are provided to evaluate the set of achievable rates and the power consumption of the proposed receiver architectures. Circuit simulations and measurement results, based on both 22 nm FDSOI CMOS technology and 65 nm Bulk CMOS transistor technologies, are provided to justify the power efficiency of the proposed receiver architectures.

Non-Linear Analog Processing in MIMO Systems with Coarse Quantization

TL;DR

The paper tackles the power bottleneck of ADCs in mmWave MIMO receivers by introducing nonlinear analog processing—envelope detectors and polynomial operators—before sampling and low-resolution quantization. It develops a unified framework linking analog front-end design to achievable rates under a total ADC power budget, derives capacity bounds and inner bounds for SISO and hybrid MIMO setups, and demonstrates how nonlinear processing can mitigate the curse of low dimensions that hampers rate scaling with the number of ADCs. The key contributions include theoretical capacity results for envelope-detector and polynomial-based front-ends, a practical hybrid-beamforming quantizer design achieving notable high-SNR gains, and circuit-level simulations and measurements across 22 nm FDSOI and 65 nm bulk CMOS showing improved rate-power tradeoffs. The findings suggest that carefully engineered nonlinear analog processing can substantially reduce rate loss due to coarse quantization while maintaining favorable power profiles, with clear guidance for mmWave receiver architectures and circuit implementations.

Abstract

Analog to digital converters (ADCs) are a major contributor to the power consumption of multiple-input multiple-output (MIMO) receivers in large bandwidth millimeter-wave systems. Prior works have considered two mitigating solutions to reduce the ADC power consumption: i) decreasing the number of ADCs via analog and hybrid beamforming, and ii) decreasing the ADC resolution, i.e., utilizing one-bit and few-bit ADCs. These mitigating solutions lead to performance loss in terms of achievable rates due to increased quantization error. In this work, the use of nonlinear analog operators such as envelope detectors and polynomial operators, prior to sampling and quantization is considered, as a way to reduce the aforementioned rate-loss. The receiver architecture consists of linear combiners, nonlinear analog operators, and few-bit ADCs. The fundamental performance limits of the resulting communication system, in terms of achievable rates, are investigated under various assumptions on the set of implementable analog operators. Extensive numerical evaluations are provided to evaluate the set of achievable rates and the power consumption of the proposed receiver architectures. Circuit simulations and measurement results, based on both 22 nm FDSOI CMOS technology and 65 nm Bulk CMOS transistor technologies, are provided to justify the power efficiency of the proposed receiver architectures.
Paper Structure (27 sections, 11 theorems, 36 equations, 11 figures)

This paper contains 27 sections, 11 theorems, 36 equations, 11 figures.

Table of Contents

  1. Introduction
  2. Problem Formulation
  3. System Model
  4. The ADC Module
  5. Conventional Beamforming Architectures
  6. Curse of Low Dimensions
  7. High SNR Capacity of Hybrid Beamforming Systems
  8. A Mitigating Solution Using Non-Linear Processing
  9. SISO Systems Equipped with Envelope Detectors
  10. Concatenated Sequences of Envelope Detectors
  11. The Quantizer and Its Associated Codebook
  12. Single Envelope Detector and One-bit Quantization
  13. Concatenated Envelope Detectors and Few-bit ADCs
  14. SISO Systems with Polynomial Operators
  15. Analog Polynomial Operators
  16. ...and 12 more sections

Key Result

Proposition 1

Let $h\neq0$, $P_{ADC}>0$, $\delta=1$, and $\ell=2$. Then, where $2\alpha$ is the unit of power consumption for a one-bit ADC.

Figures (11)

  • Figure 1: (Top) MIMO communication setup consisting of message $M$, channel input $\mathbf{X}$, channel output $\mathbf{Y}$, and message reconstruction $\widehat{M}$. (Bottom) receiver consisting of an analog processing module $\mathbf{f}_a(\cdot)$, ADC input $\mathbf{W}$, ADC module $\mathbf{a}(\cdot)$, ADC output $\mathbf{\widehat{W}}$, and a digital processing module $\mathbf{f}_{d}(\cdot)$.
  • Figure 2: (a)--(c) The Voronoi Regions for various hybrid beamforming architectures considered in Section \ref{['sec:ex1']}. (d)-(e) Voronoi regions for beamforming architectures with nonlinear analog processing in the example of Section \ref{['sec:ex1']}. Blue-colored binary vectors correspond to regions with unique ADC outputs.
  • Figure 3: The Voronoi regions and ADC outputs produced when using envelope detectors in the example of Equation \ref{['eq:exenv']}.
  • Figure 4: The quantizer outputs in Examples \ref{['ex:0']} and \ref{['Ex:1']}. The first four rows show the sign of $f_{j,k}, j\in [n_q],k\in [\ell-1]$ for $y$ within each interval, and the last row is the quantizer output.
  • Figure 5: Quantizer outputs and Voronoi regions in Example \ref{['ex:4']}.
  • ...and 6 more figures

Theorems & Definitions (18)

  • Example 1: Quantizer
  • Definition 1: Quantizer
  • Example 2: Associated Code
  • Proposition 1
  • Theorem 1
  • Example 3: Degenerate Bias Vector
  • Proposition 2: Non-Degenerate Bias Vectors
  • Definition 2: Fully-Symmetric Vector
  • Proposition 3
  • Proposition 4: Properties of the Associated Code
  • ...and 8 more