RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory

TL;DR

This paper investigates how Monolithic 3D (M3D) integration reshapes performance and energy bottlenecks, moving emphasis from main memory to the processor core and caches. By conducting a thorough design space exploration on a state-of-the-art M3D baseline, the authors derive RevaMp3D, a five-pronged redesign that removes the L2 cache, shortens L1 latency via M3D-suited SRAM layout, widens pipelines, implements register-file level synchronization, and memoizes front-end µops in M3D main memory. The evaluation shows substantial improvements, including 1.2×–2.9× speedups and 1.2×–1.4× energy reductions over the M3D baseline, plus 4.96× speedups over 2D and 7.14× over 3D baselines, along with a 12.3% area reduction. The work demonstrates that architectural choices tailored to M3D’s unique inter-layer connectivity and memory bandwidth can dramatically enhance performance and energy efficiency, offering practical guidance for hardware/software co-design in M3D systems.

Abstract

Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip, allowing for fine-grained connections between layers and significantly alleviating main memory bottlenecks. We show for a variety of workloads, on a state-of-the-art M3D-based system, that the performance and energy bottlenecks shift from main memory to the processor core and cache hierarchy. Therefore, there is a need to revisit current designs that have been conventionally tailored to tackle the memory bottleneck. Based on the insights from our design space exploration, we propose RevaMp3D, introducing five key changes. First, we propose removing the shared last-level cache, as this delivers speedups comparable to or exceeding those from increasing its size or reducing its latency across all workloads. Second, since improving L1 cache latency has a large impact on performance, we reduce L1 latency by leveraging an M3D layout to shorten its wires. Third, we repurpose the area from the removed cache to widen and scale up pipeline structures, accommodating more in-flight requests that are efficiently served by M3D memory. To avoid latency penalties from these larger structures, we leverage M3D layouts. Fourth, to facilitate high thread-level parallelism, we propose a new fine-grained synchronization technique, using M3D's dense inter-layer connectivity. Fifth, we leverage the M3D main memory to mitigate the core bottlenecks. We propose a processor frontend design that memoizes the repetitive fetched, decoded, and reordered instructions, stores them in main memory, and turns off the relevant parts of the core when possible. RevaMp3D provides 1.2x-2.9x speedup and 1.2x-1.4x energy reduction compared to a state-of-the-art M3D system. We also analyze RevaMp3D's design decisions across various memory latencies to facilitate latency-aware design decisions.

Figures (26)

• Figure 1: Systems with 2D, 3D, and M3D integration.
• Figure 2: Overview of the baseline M3D-based system aly2018n3xt.
• Figure 3: Performance benefits of the M3D-based system over the 3D and 2D systems.
• Figure 4: Bottlenecks of a latency-bound workload.
• Figure 5: Bottlenecks of a bandwidth-bound workload.