Evaluating the effects of reducing voltage margins for energy-efficient operation of MPSoCs
Diego V. Cirilo do Nascimento, Kyriakos Georgiou, Kerstin I. Eder, Samuel Xavier-de-Souza
TL;DR
This work investigates the feasibility of reducing voltage guardbands in MPSoCs by violating the GAP8's manufacturer limits while using core-redundancy-based EDAC to maintain correctness. It combines two experiments—a broad error-detection study with a PRNG and a real-world parallel satellite-communications workload—to quantify margins and energy outcomes. The results show that energy can be reduced by up to about 27% at equivalent performance, with the system surviving voltages or frequencies beyond datasheet guardbands, up to frequencies about 2.5 times the recommended maximum in some cases. The findings highlight practical routes for energy-efficient MPSoC operation via EDAC-enabled guardband reduction, while noting hardware limits (DC-DC converter and thermal effects) and the potential for approximate computing in suitable workloads.
Abstract
Voltage margins, or guardbands, are imposed on DVFS systems to account for process, voltage, and temperature variability effects. While necessary to assure correctness, guardbands reduce energy efficiency, a crucial requirement for embedded systems. The literature shows that error detection techniques can be used to maintain the system's reliability while reducing or eliminating the guardbands. This letter assesses the practically available margins of a commercial RISC-V MPSoC while violating its guardband limits. The primary motivation of this work is to support the development of an efficient system leveraging the redundancy of multicore architectures for an error detection and correction scheme capable of mitigating the errors caused by aggressive voltage margin reduction. For an equivalent performance, we achieved up to 27% energy reduction while violating the manufacturer's defined guardband, leaving reasonable energy margins for further development.