The Future of Quantum Computing with Superconducting Qubits

TL;DR

The paper argues that superconducting-qubit quantum computing sits at a critical juncture where large-scale quantum advantage will rely on quantum error correction (notably high-rate quantum LDPC codes) and non-2D connectivity, while near-term gains are achievable through error mitigation, circuit knitting, and heuristic algorithms. It introduces quantum-centric supercomputing, a modular architecture integrating QPUs with classical processors and a four-layer software stack to enable dynamic circuits, runtime optimization, and serverless deployment, all aimed at making quantum computation practical and accessible. A hardware roadmap emphasizes cycles of learning to increase fidelity, scalability, and modularity (dense, long-range, on-chip non-local, and photonic links) and argues for modularity at every level to enable large-scale, parallel quantum workloads. In the long term, the authors advocate LDPC-based fault-tolerance with non-2D topologies, supported by standardized interfaces and vendor ecosystems, to achieve ubiquitous quantum computing, while leveraging error mitigation and circuit knitting in the interim to accelerate useful demonstrations.

Abstract

For the first time in history, we are seeing a branching point in computing paradigms with the emergence of quantum processing units (QPUs). Extracting the full potential of computation and realizing quantum algorithms with a super-polynomial speedup will most likely require major advances in quantum error correction technology. Meanwhile, achieving a computational advantage in the near term may be possible by combining multiple QPUs through circuit knitting techniques, improving the quality of solutions through error suppression and mitigation, and focusing on heuristic versions of quantum algorithms with asymptotic speedups. For this to happen, the performance of quantum computing hardware needs to improve and software needs to seamlessly integrate quantum and classical processors together to form a new architecture that we are calling quantum-centric supercomputing. Long term, we see hardware that exploits qubit connectivity in higher than 2D topologies to realize more efficient quantum error correcting codes, modular architectures for scaling QPUs and parallelizing workloads, and software that evolves to make the intricacies of the technology invisible to the users and realize the goal of ubiquitous, frictionless quantum computing.

Figures (9)

• Figure 1: Estimated number of CNOT gates required to approximate the unitary evolution operator $e^{-iHt}$ for the $n$-qubit Heisenberg chain with $t=n$ and approximation error $0.001$ using randomized $k$-th order product formulas ($k=1,4,6$). The presented data is based on empirical estimates of ref. childs2019faster, see Eq. (70) therein, assuming that exponentiating a single term in the Hamiltonian costs $3$ CNOTs.
• Figure 2: Runtime scaling (number of circuit instances) needed to error mitigate 100 and 1000 Trotter steps in a circuit of 100 qubits and layers of non-overlapping two-qubit gates, each gate affected by a local depolarizing two-qubit error. The red dotted line identifies 100 million circuits, the daily limit assuming a repetition rate of 1 $ms$. So far the only architectures that have achieved this speed are solid-state based. The number of circuit instances dramatically decreases with slight improvements in the error rate of the physical gates.
• Figure 3: An example of a scheme that allows breaking the plane for signal delivery compatible with the integration of hundreds of qubits. It is composed of technologies adapted from conventional CMOS processing.
• Figure 4: Beyond classical parallelization of QPUs, shown in (a), long-range quantum connections carry a high penalty in gate speed and fidelity. As shown in (b)-(e), a high fidelity, large quantum system will likely involve three levels of modularity—a very short-range modularity m that allows breaking a QPU into multiple chips with minimal cost in gate speed and fidelity, a longer range connection l for use within a single cryogenic environment to both get around I/O bottlenecks and allow non-trivial topologies or routing, and a very long-range optical "quantum network" t to allow nearby QPUs to work together as a single quantum computational node (QCN). We will also need on-chip non-local couplers c as shown in (b) for the exploration of LDPC codes. In this figure, pink lines represent quantum communication and purple lines represent classical communication.
• Figure 5: Circuits can be represented at various levels. Unitary blocks represent circuits from libraries. These can be decomposed into parameterized circuits using the universal set of gates. Parameterized physical circuits use the physical gates supported by the hardware, while scheduled circuits specify timing, calibrations, and pulse shapes.