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CMOS-based area-and-power-efficient neuron and synapse circuits for time-domain analog spiking neural networks

Xiangyu Chen, Zolboo Byambadorj, Takeaki Yajima, Hisashi Inoue, Isao H. Inoue, Tetsuya Iizuka

TL;DR

This work proposes a neural structure for generating and transmitting time-domain signals, including a neuron module, a synapse module, and two weight modules, driven by a leakage current of MOS transistors and uses an inverter-based comparator to realize a firing function, thus providing higher energy and area efficiency compared to conventional designs.

Abstract

Conventional neural structures tend to communicate through analog quantities such as currents or voltages, however, as CMOS devices shrink and supply voltages decrease, the dynamic range of voltage/current-domain analog circuits becomes narrower, the available margin becomes smaller, and noise immunity decreases. More than that, the use of operational amplifiers (op-amps) and continuous-time or clocked comparators in conventional designs leads to high energy consumption and large chip area, which would be detrimental to building spiking neural networks. In view of this, we propose a neural structure for generating and transmitting time-domain signals, including a neuron module, a synapse module, and two weight modules. The proposed neural structure is driven by a leakage current of MOS transistors and uses an inverter-based comparator to realize a firing function, thus providing higher energy and area efficiency compared to conventional designs. The proposed neural structure is fabricated using TSMC 65 nm CMOS technology. The proposed neuron and synapse occupy the area of 127 μm^{ 2} and 231 μm^{ 2}, respectively, while achieving millisecond time constants. Actual chip measurements show that the proposed structure implements the temporal signal communication function with millisecond time constants, which is a critical step toward hardware reservoir computing for human-computer interaction. Simulation results of the spiking-neural network for reservoir computing with the behavioral model of the proposed neural structure demonstrate the learning function.

CMOS-based area-and-power-efficient neuron and synapse circuits for time-domain analog spiking neural networks

TL;DR

This work proposes a neural structure for generating and transmitting time-domain signals, including a neuron module, a synapse module, and two weight modules, driven by a leakage current of MOS transistors and uses an inverter-based comparator to realize a firing function, thus providing higher energy and area efficiency compared to conventional designs.

Abstract

Conventional neural structures tend to communicate through analog quantities such as currents or voltages, however, as CMOS devices shrink and supply voltages decrease, the dynamic range of voltage/current-domain analog circuits becomes narrower, the available margin becomes smaller, and noise immunity decreases. More than that, the use of operational amplifiers (op-amps) and continuous-time or clocked comparators in conventional designs leads to high energy consumption and large chip area, which would be detrimental to building spiking neural networks. In view of this, we propose a neural structure for generating and transmitting time-domain signals, including a neuron module, a synapse module, and two weight modules. The proposed neural structure is driven by a leakage current of MOS transistors and uses an inverter-based comparator to realize a firing function, thus providing higher energy and area efficiency compared to conventional designs. The proposed neural structure is fabricated using TSMC 65 nm CMOS technology. The proposed neuron and synapse occupy the area of 127 μm^{ 2} and 231 μm^{ 2}, respectively, while achieving millisecond time constants. Actual chip measurements show that the proposed structure implements the temporal signal communication function with millisecond time constants, which is a critical step toward hardware reservoir computing for human-computer interaction. Simulation results of the spiking-neural network for reservoir computing with the behavioral model of the proposed neural structure demonstrate the learning function.
Paper Structure (5 figures, 1 table)

This paper contains 5 figures, 1 table.

Figures (5)

  • Figure 1: (a) The proposed structure and (b) a micrograph of the chip.
  • Figure 2: (a) Circuit diagram of the proposed neuron module, (b) behaviours of proposed LIF neuron and synapse modules, (c) circuit diagram of the proposed synapse module, and (d) circuit diagram of the proposed weight module.
  • Figure 3: (a) A photo of the experimental setup, (b) the measured firing rate of the neuron for 4 chips, (c) the measured waveforms of the neuron output, and (d) the measured waveforms of the synapse output.
  • Figure 4: (a) Another combined structure fabricated to evaluate the synapse and (b) the measured waveforms of $V_{\mathrm{Ring}}$ and $V_{\mathrm{SYN}}$.
  • Figure 5: (a) The behavioral model of the SNN for reservoir computing based on the proposed neural structure. (b) The system-level behavioral simulation results: (i) based on a model with $15$ Hz$- 200$ Hz frequency tuning range, zoomed-in view of the (ii) excitatory and (iii) inhibitory input signals converted from the output, (iv) based on $15$ Hz$- 2$ kHz and (v)$15$ Hz$- 20$ kHz frequency tuning ranges.