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Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects

Ralf Ramsauer, Stefan Huber, Konrad Schwarz, Jan Kiszka, Wolfgang Mauerer

TL;DR

This work focuses on exploiting contemporary virtualisation mechanisms to achieve freedom from interference respectively isolation between workloads, and presents findings on the current RISC-V specification and its implementations that necessitate interventions of superordinate control structures.

Abstract

On embedded processors that are increasingly equipped with multiple CPU cores, static hardware partitioning is an established means of consolidating and isolating workloads onto single chips. This architectural pattern is suitable for mixed-criticality workloads that need to satisfy both, real-time and safety requirements, given suitable hardware properties. In this work, we focus on exploiting contemporary virtualisation mechanisms to achieve freedom from interference respectively isolation between workloads. Possibilities to achieve temporal and spatial isolation-while maintaining real-time capabilities-include statically partitioning resources, avoiding the sharing of devices, and ascertaining zero interventions of superordinate control structures. This eliminates overhead due to hardware partitioning, but implies certain hardware capabilities that are not yet fully implemented in contemporary standard systems. To address such hardware limitations, the customisable and configurable RISC-V instruction set architecture offers the possibility of swift, unrestricted modifications. We present findings on the current RISC-V specification and its implementations that necessitate interventions of superordinate control structures. We identify numerous issues adverse to implementing our goal of achieving zero interventions respectively zero overhead: On the design level, and especially with regards to handling interrupts. Based on micro-benchmark measurements, we discuss the implications of our findings, and argue how they can provide a basis for future extensions and improvements of the RISC-V architecture.

Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects

TL;DR

This work focuses on exploiting contemporary virtualisation mechanisms to achieve freedom from interference respectively isolation between workloads, and presents findings on the current RISC-V specification and its implementations that necessitate interventions of superordinate control structures.

Abstract

On embedded processors that are increasingly equipped with multiple CPU cores, static hardware partitioning is an established means of consolidating and isolating workloads onto single chips. This architectural pattern is suitable for mixed-criticality workloads that need to satisfy both, real-time and safety requirements, given suitable hardware properties. In this work, we focus on exploiting contemporary virtualisation mechanisms to achieve freedom from interference respectively isolation between workloads. Possibilities to achieve temporal and spatial isolation-while maintaining real-time capabilities-include statically partitioning resources, avoiding the sharing of devices, and ascertaining zero interventions of superordinate control structures. This eliminates overhead due to hardware partitioning, but implies certain hardware capabilities that are not yet fully implemented in contemporary standard systems. To address such hardware limitations, the customisable and configurable RISC-V instruction set architecture offers the possibility of swift, unrestricted modifications. We present findings on the current RISC-V specification and its implementations that necessitate interventions of superordinate control structures. We identify numerous issues adverse to implementing our goal of achieving zero interventions respectively zero overhead: On the design level, and especially with regards to handling interrupts. Based on micro-benchmark measurements, we discuss the implications of our findings, and argue how they can provide a basis for future extensions and improvements of the RISC-V architecture.
Paper Structure (17 sections, 2 figures)

This paper contains 17 sections, 2 figures.

Table of Contents

  1. Introduction
  2. Related Work
  3. Architecture
  4. Jailhouse: Concepts and Rationale
  5. RISC-V Platform Virtualisation
  6. Virtualisation Architecture
  7. Memory Management
  8. Interrupt Controller
  9. Hyperthreading
  10. Evaluation
  11. Benchmarking Setup
  12. Benchmark #1---IRQ Reinjection
  13. Benchmark #2---IPI Round Trip Time
  14. Benchmark #3---PLIC Emulation
  15. Benchmark #4---Synchronous Traps
  16. ...and 2 more sections

Figures (2)

  • Figure 1: Illustration of the cross-systems code path for our benchmarks. Dots/squares mark traps; squares are unavoidable, while dots arise from HV interaction. For the IPI round trip measurement (teal), the path is also traversed in backward direction, as indicated by the loop. The additional load in the Linux domain to perturb the measurement is optional, and only generated in scenario (C).
  • Figure 2: Measurement Results (notice the double logarithmic axes): CPU cycles taken for our benchmarks---comparing performance bare-metal vs. with hypervisor (with and without load on other cores).