On Matrix Multiplication and Polynomial Identity Testing
Robert Andrews
TL;DR
This work establishes a direct link between border-rank lower bounds for $n\times n\times n$ matrix multiplication and derandomization of polynomial identity testing for small algebraic circuits. By lifting border-rank lower bounds to border multiplicative complexity bounds for polynomials in determinantal ideals via trace ABPs and determinant-cycle constructions, the authors obtain explicit hitting-set generators with seed lengths $O\left(\sqrt{n}\,\underline{R}^{-1}(s)\right)$ and unconditional $O(\sqrt{ns})$ bounds. Under the hypothesis $\omega>2$, these generators yield nontrivial PIT algorithms for circuits of size $O(n^{1+\delta})$ with seed lengths $O(n^{1-\varepsilon})$, while if $\omega=2$, the approach would imply extremely fast algorithms for matrix multiplication and related problems. Overall, the paper advances the hardness-randomness paradigm by tying algebraic circuit lower bounds to pseudorandomness constructions in a setting close to unconditional derandomization for small multiplicative complexity. The results are significant in that they provide the first nontrivial hitting-set constructions for circuits with sublinear multiplicative complexity and bring unconditional progress on PIT closer to known hardness assumptions.
Abstract
We show that lower bounds on the border rank of matrix multiplication can be used to non-trivially derandomize polynomial identity testing for small algebraic circuits. Letting $\underline{R}(n)$ denote the border rank of $n \times n \times n$ matrix multiplication, we construct a hitting set generator with seed length $O(\sqrt{n} \cdot \underline{R}^{-1}(s))$ that hits $n$-variate circuits of multiplicative complexity $s$. If the matrix multiplication exponent $ω$ is not 2, our generator has seed length $O(n^{1 - \varepsilon})$ and hits circuits of size $O(n^{1 + δ})$ for sufficiently small $\varepsilon, δ> 0$. Surprisingly, the fact that $\underline{R}(n) \ge n^2$ already yields new, non-trivial hitting set generators for circuits of sublinear multiplicative complexity.